12 July 2002 Wafer-level fault detection and classification on a photo track in a high volume fab
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Abstract
We will discuss Advanced Micro Devices's (AMD) Fault Detection and Classification (FDC) program strategy and our six-step project template that we have identified that must be addressed for any successful FDC effort. We will discuss the recent development and implementation of a wafer-level FDC system on a TEL CLEAN TRAC ACT 8 photo track system in AMD's Fab25, a high volume microprocessor factory. We will present our approach to designing and implementing this FDC system and demonstrate its ability to automatically identify specific wafers within a lot that require manual review. Upon manual review, the decision can be made to rework the specific wafers or the lot.
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Timothy L. Jackson, Richard J. Markle, Clinton W. Miller, Edward C. Stewart, Robert A. Crowell, "Wafer-level fault detection and classification on a photo track in a high volume fab", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475649; https://doi.org/10.1117/12.475649
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