Enriching design intent for optimal OPC and RET

Michael L. Rieger; Valery Gravoulet; Jeffrey P. Mayhew; Daniel F. Beale; Robert M. Lugg

doi:10.1117/12.476939

1 August 2002 Enriching design intent for optimal OPC and RET

Michael L. Rieger, Valery Gravoulet, Jeffrey P. Mayhew, Daniel F. Beale, Robert M. Lugg

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Proceedings Volume 4754, Photomask and Next-Generation Lithography Mask Technology IX; (2002) https://doi.org/10.1117/12.476939
Event: Photomask and Next Generation Lithography Mask Technology IX, 2002, Yokohama, Japan

Abstract

In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.

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Michael L. Rieger, Michael L. Rieger, Valery Gravoulet, Valery Gravoulet, Jeffrey P. Mayhew, Jeffrey P. Mayhew, Daniel F. Beale, Daniel F. Beale, Robert M. Lugg, Robert M. Lugg, } "Enriching design intent for optimal OPC and RET", Proc. SPIE 4754, Photomask and Next-Generation Lithography Mask Technology IX, (1 August 2002); doi: 10.1117/12.476939; https://doi.org/10.1117/12.476939

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