19 April 2002 On-chip synchronous detection for CMOS BDJ optical detector
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Proceedings Volume 4755, Design, Test, Integration, and Packaging of MEMS/MOEMS 2002; (2002) https://doi.org/10.1117/12.462813
Event: Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS 2002, 2002, Cannes-Mandelieu, France
Abstract
On-chip electronics performing weak-signal recovery for CMOS BDJ (Buried Double p-n Junction) optical detector is proposed. It includes two identical channels for simultaneous processing of both detector's output signals in continuous-time configuration. Each channel consists of a transimpedance amplifier, a fully differential amplifier, a multiplier and a low-pass filter, thus performing low-noise preamplification and synchronous demodulation. Some key building blocks have been designed with performance optimization. In order to validate the proposed architecture, to verify the system operation and to estimate its performances and characteristics, system-level simulations have been carried out. It has been evaluated that, in a typical case, the integrated system can detect an input optical signal of 21 fW/mm2.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guo Neng Lu, Gerard Sou, A. Aubert, G. Carrillo, A. El Mourabit, "On-chip synchronous detection for CMOS BDJ optical detector", Proc. SPIE 4755, Design, Test, Integration, and Packaging of MEMS/MOEMS 2002, (19 April 2002); doi: 10.1117/12.462813; https://doi.org/10.1117/12.462813
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