16 August 2002 Pattern data processing using 1-nm address grid
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Proceedings Volume 4764, 18th European Conference on Mask Technology for Integrated Circuits and Microcomponents; (2002) https://doi.org/10.1117/12.479333
Event: 18th European Mask Conference on Mask Technology for Integrated Circuits and Micro-Components, 2002, Munich-Unterhaching, Germany
Abstract
In the past years the address grid for layout design, data preparation and exposure has been constantly reduced. Currently the ITRS Roadmap specifies 4nm Mask Design Grid for the 100nm technology node. The possibilities and challenges of pattern data processing for the new generation of Leica's Shaped Beam (SB) exposure tools, called SB350MW, are highlighted in this paper. In this context such issues like data volume, data processing time and fracture quality for the new 1nm pattern data format are discussed in detail.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Juergen Gramss, Juergen Gramss, Hans Eichhorn, Hans Eichhorn, Michael Gehre, Michael Gehre, Bernd Schnabel, Bernd Schnabel, Traugott Schulmeiss, Traugott Schulmeiss, Detlef Melzer, Detlef Melzer, Klaus Kunze, Klaus Kunze, Ulrich Baetz, Ulrich Baetz, } "Pattern data processing using 1-nm address grid", Proc. SPIE 4764, 18th European Conference on Mask Technology for Integrated Circuits and Microcomponents, (16 August 2002); doi: 10.1117/12.479333; https://doi.org/10.1117/12.479333
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