Translator Disclaimer
16 August 2002 Review of the 2001 ITRS update
Author Affiliations +
Proceedings Volume 4764, 18th European Conference on Mask Technology for Integrated Circuits and Microcomponents; (2002)
Event: 18th European Mask Conference on Mask Technology for Integrated Circuits and Micro-Components, 2002, Munich-Unterhaching, Germany
In 1992 the SIA published the first roadmap for semiconductors. Since then formal updates have been published in 1994, 1997, 1999 and now 2001. The 2001 ITRS update will not be published until Dec. 2001 so the tables in this document may change in the final release. The complete 2001 update can be found at: http:/'/pubiic.i.trsnet/ Sinc e the earliest days of the microelectronics industry, optical lithography has been the mainstream technology for volume manufacturing, and it is expected to continue as such through the 65 nm node, through the application of resolution enhancement techniqies such as off-axis illumination (OAI), phase shifting masks (PSM) and optical proximity corrections (OPC). In addition to resolution enhancement techniques, wavelength reductions (248 nnr 193 nm-) 157 nm) and lenses with increasing numerical apertures and decreasing aberrations will be required to extend the life of optical lithography. The requirements of the 45 nm node and beyond are viewed as beyond the capabilities of optical lithography. Extension of the Roadmap will require the development of next- generation lithography (NGL) technologies, such extreme ultraviolet lithography (EUV) and electron projection lithography (EPL). Because next generation lithographies will require the development of substantially new infrastructure, the costs of these technolo gies will put great pressure on manufacturing costs. Mask-making capability and cost escalation have become the major limiter to lithography progress. The roadmap acceleration has been very troublesome to the mask industry. CD control is falling behind the requirements of the chipmakers Where it might be said that the mask makers have been hit by the "perfect storm". First the two year cycle has reduced the available time for development, Secondly the gate widths post etch for MPU's have reduced even Ihster, And finally the mask industry has been asked to absorb the entire impact of the increased MEF associated with Low Kl Lithography. Mask equipment and process capabilities are in manufacturing for complex OPC and PSM.. Mask processes for Post 193nm technologies are in research and development.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gilbert V. Shelden "Review of the 2001 ITRS update", Proc. SPIE 4764, 18th European Conference on Mask Technology for Integrated Circuits and Microcomponents, (16 August 2002);


New mask technology challenges
Proceedings of SPIE (September 05 2001)
Patterning strategy for low-K<sub>1</sub> lithography
Proceedings of SPIE (August 20 2004)

Back to Top