6 December 2002 Design of a hybrid prefix adder for nonuniform input arrival times
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This paper examines the design of a hybrid prefix adder under the condition of non-uniform input signal arrival. This is encountered in the final adder for fast parallel multipliers, which use column compression reduction. The prefix graph scheme efficiently accommodates the non-uniform arrival times. Rules are presented for designing hybrid prefix adders under such conditions. This rule produces adders which are faster and less complex than previous work.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Youngmoon Choi, Earl E. Swartzlander, "Design of a hybrid prefix adder for nonuniform input arrival times", Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452040; https://doi.org/10.1117/12.452040


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