Number representation optimization for low-power multiplier design

Zhijun Huang; Milos D. Ercegovac

doi:10.1117/12.452045

Abstract

Multipliers using different number representation systems have different power/area/delay characteristics. This paper studies the effects of number representations on power consumption and proposes optimization techniques for two's-complement multipliers. By examining existing radix-4 recoding design schemes, two power-improved designs are proposed for standard cell CMOS technology. With new recoding schemes, the power efficiency of radix-4 multipliers versus radix-2 multipliers are re-investigated. To utilize the power efficiency of sign-magnitude representation, number representation conversion schemes are proposed. For a typical data set from application djpeg, the conversion schemes consume less than 30% power of the baseline schemes.

Citation Download Citation

Zhijun Huang, Zhijun Huang, Milos D. Ercegovac, Milos D. Ercegovac, } "Number representation optimization for low-power multiplier design", Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452045; https://doi.org/10.1117/12.452045

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