6 December 2002 Packed arithmetic on a prefix adder (PAPA)
Author Affiliations +
Abstract
This paper describes a new method for performing packed arithmetic on a prefix adder that enables sub-wordlength additions and subtractions to be performed in parallel on any prefix adder topology. A major benefit of the proposed technique is that the critical path length of the prefix carry tree is unaltered when measured as the number of complex CMOS logic gates. Moreover, there is no restriction on the prefix tree's cell topology and the adder is also capable of performing packed absolute difference and packed rounded average calculations.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Neil Burgess, Neil Burgess, } "Packed arithmetic on a prefix adder (PAPA)", Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.453812; https://doi.org/10.1117/12.453812
PROCEEDINGS
10 PAGES


SHARE
RELATED CONTENT

An Ultra-Fast SBNR Divider
Proceedings of SPIE (May 16 1989)
Computer arithmetic for the processing of media signals
Proceedings of SPIE (November 12 2000)
Classification of multimedia processors
Proceedings of SPIE (December 20 1998)

Back to Top