6 December 2002 Parametric time delay modeling for floating point units
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A parametric time delay model to compare floating point unit implementations is proposed. This model is used to compare a previously proposed floating point adder using a redundant number representation with other high-performance implementations. The operand width, the fan-in of the logic gates and the radix of the redundant format are used as parameters to the model. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation.
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Hossam A. H. Fahmy, Hossam A. H. Fahmy, Albert A. Liddicoat, Albert A. Liddicoat, Michael J. Flynn, Michael J. Flynn, } "Parametric time delay modeling for floating point units", Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452014; https://doi.org/10.1117/12.452014

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