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2 July 2002 Design flow for the reconfigurable HW platform XPP
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Proceedings Volume 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV; (2002) https://doi.org/10.1117/12.455385
Event: ITCom 2002: The Convergence of Information Technologies and Communications, 2002, Boston, MA, United States
Abstract
Due to an increasing technology progress in the configurable hardware sector, which is currently dominated by FPGAs, new approaches like very fast re-configurable devices with ALU level granularity are on the rise. However, these coprocessor devices can not be programmed with conventional HW nor SW design approaches. To solve this dilemma, a combination is needed. This approach is described in this paper. Furthermore, an example how to program a re-configurable device is illustrated. This example consists of parts of an MPEG-4 decoder, which is running on the re-configurable processor platform XPP. The partitioning of these decoding algorithms into modules and the means of interaction between these modules is highlighted. In addition, the embedding of this algorithm in a XPP system is outlined.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Claus Ritter, Eberhard Schueler, Eric Sax, and Klaus-Dieter Mueller-Glaser "Design flow for the reconfigurable HW platform XPP", Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); https://doi.org/10.1117/12.455385
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