Correction of geometric image distortion using FPGAs

David Eadie; Fergal P. Shevlin; Andy Nisbet

doi:10.1117/12.463765

19 March 2003 Correction of geometric image distortion using FPGAs

David Eadie, Fergal P. Shevlin, Andy Nisbet

Proceedings Volume 4877, Opto-Ireland 2002: Optical Metrology, Imaging, and Machine Vision; (2003) https://doi.org/10.1117/12.463765
Event: OPTO Ireland, 2002, Galway, Ireland

Abstract

Many image processing systems have real-time performance constraints. Systems implemented on general purpose processors maximize performance by keeping busy the small fixed number of available functional units such as adders and multipliers. In this paper we investigate the use of programmable logic devices to accelerate the execution of an application. Field Programmable Gate Arrays (FPGAs) can be programmed to generate application specific logic that alters the balance and type(s) of functional units to match application characteristics. In this paper we introduce a correction of geometric image distortion application. Real number support is a requirement in most image processing applications. We examine the suitability of fixed point, floating-point and logarithmic number systems for an FPGA implementation of this image processing application. Performance results are presented in terms of: (1) execution time, and (2) FPGA logic resource requirements.

Citation Download Citation

David Eadie, Fergal P. Shevlin, and Andy Nisbet "Correction of geometric image distortion using FPGAs", Proc. SPIE 4877, Opto-Ireland 2002: Optical Metrology, Imaging, and Machine Vision, (19 March 2003); https://doi.org/10.1117/12.463765

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