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27 December 2002 Fast Full-Chip MEEF Simulations for Mask and Wafer Metrology
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Abstract
Simulation-based techniques assisted mask and wafer metrology and inspection have become increasingly important with the growth of the sub-wavelength gap in optical photolithography. This paper describes a method for full-chip layout verification based on fast calculation of the mask error enhancement factor (MEEF). Because of the significant amount of MEEF computations necessary for large layouts, we discuss a methodology that takes advantage of distributed computing environment to significantly shorten the total run time. Additionally, MEEF calculations can be selectively reduced to layout locations that meet specific criteria, which allows to not only reduce the overall simulation time, but also to decrease the output data volume transferred to the mask inspection equipment. After MEEF is calculated, a SQL database is used to generate a summary report and to efficiently locate high-MEEF areas, which could be sent in a form marker files to metrology tools.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chi-Ming Tsai, Hua-Yu Liu, Armen Kroyan, Ning-Chuan Shen, and Yao-Ting Wang "Fast Full-Chip MEEF Simulations for Mask and Wafer Metrology", Proc. SPIE 4889, 22nd Annual BACUS Symposium on Photomask Technology, (27 December 2002); https://doi.org/10.1117/12.467851
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