27 December 2002 No-fault assurance: linking fast process CAD and EDA
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Abstract
A prototype system is proposed for incorporating fast process models with EDA management of layout to identify and help arbitrate locations in a chip that are likely subject to less than ideal process effects. The approach uses pattern matching to find those locations in a layout that have the greatest impact from residual imperfections in manufacturing. For each process under study, the maximal lateral test pattern that maximizes the spillover from the surrounding pattern is first determined. The quantitative impact of the spillover for an actual layout is then assessed through comparing the degree of similarity of the actual pattern in a neighborhood about a critical point to the maximal lateral test pattern and scaling the impact accordingly. This fast-CAD pattern-matching approach is shown to be applicable for analysis of yield reduction due to combined effects of defects and alignment tolerances among mask levels as well as for identifying layout areas affected by reflective notching, CMP dishing and, with less accuracy, heating in laser assisted processing.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrew R. Neureuther, Andrew R. Neureuther, Frank E. Gennari, Frank E. Gennari, } "No-fault assurance: linking fast process CAD and EDA", Proc. SPIE 4889, 22nd Annual BACUS Symposium on Photomask Technology, (27 December 2002); doi: 10.1117/12.467898; https://doi.org/10.1117/12.467898
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