20 September 2002 CMOS APS digital camera based on enhanced parallel port
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CMOS APS become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor analogue circuitry, and digital processing functions. This paper discusses a CMOS digital camera based on EPP interface. A CMOS APS (OV7110) with VGA resolution (640 x 480) was selected as the image sensor, it can generate digital output of typically an 8 or 16 bit data bus in YUV or RGB mode, all the image controllling, e.g. frame rate, white balance, gamma control and exposure control all can be adjusted through 12C bus. The 12C bus control unit, FIFO and EPP interface, etc. are all integrated within a CPLD. The overall structure, working scheme and performance analyses of the camera were discussed in detail. Several images taken by the camera are provided and a detailed discussion of its quality, processing of image data, etc. is also given.
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Zhi Liu, Jingyi Yang, Yefan Wang, Zhihang Hao, "CMOS APS digital camera based on enhanced parallel port", Proc. SPIE 4919, Advanced Materials and Devices for Sensing and Imaging, (20 September 2002); doi: 10.1117/12.471882; https://doi.org/10.1117/12.471882


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