Processing study of next generation substrate

Yung-Ming Chang; Chih-Hao Chou; Hung-Yi Lin; Tung-Chuan Wu; Thomas Hsieh

doi:10.1117/12.469186

13 November 2002 Processing study of next generation substrate

Yung-Ming Chang; Chih-Hao Chou; Hung-Yi Lin; Tung-Chuan Wu; Thomas Hsieh;

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Proceedings Volume 4934, Smart Materials II; (2002) https://doi.org/10.1117/12.469186
Event: SPIE's International Symposium on Smart Materials, Nano-, and Micro- Smart Systems, 2002, Melbourne, Australia

Abstract

Silicon on Insulator (SOI) technologies will play a major role for low-voltage, low-power device and MEMS in semiconductor developments. Today four main material technologies, BESOI, SIMOX, Smart Cut and ELO were developed but like BESOI substrate making process has simple steps and less equipment in vestment than others. This paper presents SOI wafer fabricated by direct heat-bonded method, thermally oxidizied Si wafer as handle layer and another prime Si wafer as device layer. By the ductile mode grinding and subsequent polishing methods to fabricate the desired device layer more than 10μm and quality of total thickness variation to be 3μm, roughness 5Å. Excellent quality of bonding SOI wafer with oxidation structure which act as etch stop or sacrificed layer at processes would be widely applied in MEMS, MOS, Optical Device and so on.

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Yung-Ming Chang, Chih-Hao Chou, Hung-Yi Lin, Tung-Chuan Wu, Thomas Hsieh, "Processing study of next generation substrate", Proc. SPIE 4934, Smart Materials II, (13 November 2002); doi: 10.1117/12.469186; https://doi.org/10.1117/12.469186

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