14 November 2002 Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET
Author Affiliations +
In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (MG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 2V in the main gate 50nm. Also, we know that optimum side gate length for each main gate length is 70nm above. DG MOSFET shows a small threshold voltage (Vth) roll-off. From the I-V characteristics, we obtained IDsat=510μA/μm at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86mV/decade, transconductance is 111μA/V and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Also, we have presented that TCAD simulator is suitable for device simulation.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jae-hong Kim, Jae-hong Kim, Geun-ho Kim, Geun-ho Kim, Suk-woong Ko, Suk-woong Ko, Hak-kee Jung, Hak-kee Jung, } "Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET", Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); doi: 10.1117/12.469072; https://doi.org/10.1117/12.469072

Back to Top