14 November 2002 Threshold logic parallel counters for 32-bit multipliers
Author Affiliations +
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Celinski, Sorin D. Cotofana, Derek Abbott, "Threshold logic parallel counters for 32-bit multipliers", Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); doi: 10.1117/12.477382; https://doi.org/10.1117/12.477382


Signal Processing Of Ultra Wideband Data Streams Use Of...
Proceedings of SPIE (November 28 1983)
CMOS/SOS LSI For Real-Time Signal Processing
Proceedings of SPIE (September 21 1979)
Arithmetic processor design for the T9000 transputer
Proceedings of SPIE (December 01 1991)
Built-in self-test for high-speed integrated circuits
Proceedings of SPIE (September 12 1996)
VLSI digital signal processing: some arithmetic issues
Proceedings of SPIE (October 22 1996)

Back to Top