3 April 2003 Planar integrated free-space optics for coupling and fan-in/-out in a low-latency processor memory interconnection
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Abstract
In computer architecture bandwidth and memory latency represent a major bottleneck. One possibility for solving these problems is the use of optical interconnections with their inherent capability for large fanin and fanout, low skew, etc. Today the possibilities to produce integrated chips with optical and electronic connections are advanced and the barrier for their adoption in computer systems gets smaller. The European Union project 'High-Speed Opto-Electronic Memory Systems' (HOLMS) aims at demonstrating the feasibility of an optical bus system for CPU memory access. The bus system is based on planar integrated free-space optics (PIFSO) in combination with fibre and PCB integrated waveguide optics. The goal is to demonstrate a novel architecture of low latency memory access. Here, we will discuss the task of the free-space optics. The assignment of the PIFSO is to perform all fanin and fanout operations for the interconnection between CPU and memory. Longer distances like connections between CPU and memory will be broadcasted by waveguides in the PCB; and fibres are used to combine two PCBs to a multiprocessor system. The first task consists of the design and the realization of the interface between the PIFSO and the PCB integrated waveguides. Besides the optical coupling, it is the main aspect to find an optical solution that allows large mechanical tolerances in the packaging of the different parts of the system. The large number of optical lines and their fanout and fanin are a challenge for design and construction, too. Design issues will be discussed and first experimental results will be presented.
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Manfred Jarczynski, Manfred Jarczynski, Matthias Gruber, Matthias Gruber, Jürgen Jahns, Jürgen Jahns, } "Planar integrated free-space optics for coupling and fan-in/-out in a low-latency processor memory interconnection", Proc. SPIE 4944, Integrated Optical Devices: Fabrication and Testing, (3 April 2003); doi: 10.1117/12.470343; https://doi.org/10.1117/12.470343
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