1 August 2003 Realization of a real-time data flow acquisition and edge detection
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Proceedings Volume 4948, 25th International Congress on High-Speed Photography and Photonics; (2003) https://doi.org/10.1117/12.516724
Event: 25th international Congress on High-Speed photography and Photonics, 2002, Beaune, France
The new technologies that are CMOS sensors and most recent FPGA platform like the Xilinx Virtex-II family allow the realization of totally digital active video sensors. On the other hand, the digital visual interface (hereinafter DVI) specification provides a high-speed digital connection for visual data (T.M.D.S). These various technologies led us define a frame grabber -- processing -- display system based on three components: a CMOS sensor PB-MV13 of Photobit, a FPGA platform Virtex-II from Xilinx and a T.M.D.S transmitter SiI 160 of Silicon Image. An advantage of this realization is the suppression of the various analogue-digital conversion stages generally used to digitize and restore the video stream. The reconfiguration of the FPGA platform is another advantage, which does not limit processing to a particular purpose and simplify the conception. Besides, an important constraint of this realization is the frame definition 1280 x 1024 (SXGA) and the rate of 60 images per second with a pixel frequency of 108 MHz.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philippe Lamaty, Federic De Melo, and Cedric Munoz "Realization of a real-time data flow acquisition and edge detection", Proc. SPIE 4948, 25th International Congress on High-Speed Photography and Photonics, (1 August 2003); doi: 10.1117/12.516724; https://doi.org/10.1117/12.516724


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