Wafer thinning for high-density through-wafer interconnects

Lianwei Wang; Cassan C. G. Visser; Charles R. de Boer; M. Laros; W. van der Vlist; J. Groeneweg; G. Craciun; Pasqualina M. Sarro

doi:10.1117/12.473374

15 January 2003 Wafer thinning for high-density, through-wafer interconnects

Lianwei Wang, Cassan C. G. Visser, Charles R. de Boer, M. Laros, W. van der Vlist, J. Groeneweg, G. Craciun, Pasqualina M. Sarro

Author Affiliations +

Proceedings Volume 4979, Micromachining and Microfabrication Process Technology VIII; (2003) https://doi.org/10.1117/12.473374
Event: Micromachining and Microfabrication, 2003, San Jose, CA, United States

Abstract

Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

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Lianwei Wang, Cassan C. G. Visser, Charles R. de Boer, M. Laros, W. van der Vlist, J. Groeneweg, G. Craciun, and Pasqualina M. Sarro "Wafer thinning for high-density, through-wafer interconnects", Proc. SPIE 4979, Micromachining and Microfabrication Process Technology VIII, (15 January 2003); https://doi.org/10.1117/12.473374

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