7 May 2003 Design of low-power lifting-based coprocessor for mobile multimedia applications
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Abstract
This paper presents an efficient VLSI implementation of a lifting coprocessor for mobile multimedia applications. To reduce the hardware complexity, we designed and implemented rational lifting coefficients. This approach allows the floating-point arithmetic units to be replaced by the integer arithmetic units in the design. Consequently, footprint and power consumption of the coprocessor are reduced. To improve the throughput of system, a fully pipelined parallel architecutre is designed. With the rational coefficients and parallel approaches, the proposed lifting coprocessor provides efficient computing power but requires very low power consumtion. The lifitng scheme coprocessor was implemented in VHDL using HCMOS8D 0.18 μm technology. It can run at 25 MHz withthe power supply of 1.55 volt and requires only 1.191 mW.
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Philip P. Dang, Philip P. Dang, Paul M. Chau, Paul M. Chau, } "Design of low-power lifting-based coprocessor for mobile multimedia applications", Proc. SPIE 5022, Image and Video Communications and Processing 2003, (7 May 2003); doi: 10.1117/12.476233; https://doi.org/10.1117/12.476233
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