16 June 2003 Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction
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Proceedings Volume 5037, Emerging Lithographic Technologies VII; (2003); doi: 10.1117/12.482336
Event: Microlithography 2003, 2003, Santa Clara, California, United States
With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Laurent Pain, Murielle Charpin, Yves Laplanche, David Herisson, J. Todeschini, Ramiro Palla, A. Beverina, H. Leininger, S. Tourniol, M. Broekaart, Emmanuelle Luce, F. Judong, K. Brosselin, Y. Le Friec, F. Leverd, S. Del Medico, V. De Jonghe, Daniel Henry, M. P. Woo, F. Arnaud, "Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction", Proc. SPIE 5037, Emerging Lithographic Technologies VII, (16 June 2003); doi: 10.1117/12.482336; https://doi.org/10.1117/12.482336


Electron beam lithography


Semiconducting wafers

Optical alignment



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