We demonstrate imaging interferometric microscopy (IIM) for binary objects in two dimensions. Combining multiple exposures with different off-axis illumination configurations together with interferometric restoration of the zero-order beam during dark-field conditions, IIM provides high lateral resolution at low numerical apertures (NA). It retains the large field-of-view, long working distance and large depth-of-field of a low-NA imaging system. Also we include a first demonstration of imaging of a phase mask. All these properties are increasingly important for in semiconductor mask metrology. IIM relies on image processing to reconstruct the image; we present the processes necessary to obtain the combined image. Finally we compare the experiment with a simple Fourier optics model.

The quality assurance for production of optical components for EUV lithography strongly requires at-wavelength metrology. Presently, at-wavelength characterizations of mirrors and masks are done using the synchrotron radiation of electron storage rings, e.g. BESSY II. For the production process of EUV optics, however, the immediate access to metrology tools is necessary and availability of laboratory devices is mandatory. Within the last years a stand alone laboratory EUV reflectometer for large samples has been developed It consists of a laser produced plasma (LLP) radiation source, a monochromator and a large goniometer systme. The manipulation system of the reflectometer can handle samples with diameters of up to 500 mm, thicknesses of up to 200 mm and weights of up to 30 kg. The wavelength can be varied from 10 nm to 16 nm. The spot size on the sample surface is about 2mm. The angle of incidence can be varied from 3° to 60°. In this paper, we describe the laboratory reflectometer in detail and discuss the achieved performance. First measurements of 4 inch mirrors are presented and discussed in comparison to the results obtained at the PTB soft x-ray radiometry beamline at BESSY II.

The measurement of organic and inorganic contaminants in photolithography purge gas is validated to below a 1 part-per-trillion lower detection limit using a Cold Trap concentrated method. To investigate the contaminant loading history into a purifier during its lifetime, a Purifier Information Retrieval Service (PIRS) is developed with measurement sensitivity below 0.01 microgram. This method is validated by accurately loading and unloading known challenges of contaminants into a GateKeeper purifier. The result indicates that if a purifier is operating at 100% duty cycle and 1 slm for 1 year, an annual quantitative measurement average of the impurites in the process gas of less than 5 part-per-quadrillion can be achieved.

As the semiconductor industry continues to scale down critical dimensions (CD), proximity effects get more and more severe. As such, aggressive Optical Proximity Correction (OPC) features like hammerheads, serifs and assist bars inevitably appear on fabricated masks. The great challenge, however -- to reliably assure the quality of these advanced masks -- is to be able to direclty judge a controversial defect under such complex features. It is necessary to find a more effective way to accurately disposition the defects found on these masks. Simulation-based defect disposition strategies have now become much more important for judging defect printabiilty. In this paper, we use variaous simulation tools to make a systematic study of defect printability right from the design to wafer printing. Four different combinations of OPC features with assist bars are presented here to demonstrate the defect printability and their induced CD changes compared to wafer results.

New configuration is presented for ultra-fast at-wavelength inspection of defects on multilayer mask blanks. Key ideas are detecting defects in a high NA dark-field observation by using a Schwarzschild objective, sub-micron resolution 2D imaging of mask surface on a detector, and large etendue illumination by using a laser-plasma source. Expected time for inspecting a whole mask is shorter than 2 hours.

With each new technology node, the corresponding overlay requirements become tighter. It has been shown that differences can exist between the pattern placement error of the relatively large frame in frame type overlay structures typically used for overlay measurement and control and real device structures. These differences can become a significant part of the total overlay budget. It is therefore necessary to identify the magnitude of these differences and establish whether they can be corrected. In order to investigate these differences in pattern placement error, an alternative metrology technique needed to be established which was capable of measuring the overlay of real device structures. In the first part of this paper we show that CD SEM Overlay Metrology offers comparable precision to that of the more traditional measurement of large frame in frame type overlay structures on an optical overlay tool. In the second part of the paper we apply this metrology technique to evaluate the pattern placement errors across the field of a step and scan exposure tool for different illumination modes. This is then compared to that obtained using the more traditional optical overlay metrology technique. Finally we discuss how these differences can be handled in a production environment in order to obtain optimum overlay performance.

We have previously reported on an overlay metrology simulation platform, used for modeling both the effects of overlay metrology tool behavior and the impact of target design on the ultimate metrology performance. Since our last report, the simulation platform has been further enhanced, consisting now of eleven PCs and running commercial software both for lithography (PROLITH) and rigorous Maxwell calculations (EM-Suite). In this paper we report on the validation of the metrology simulations by comparing them to both analytical calculations and to experimental results. The analytical validation is based on the classical calculation of the diffraction of a polarized plane wave from a perfectly conducting half plane. For the experimental validation, we chose an etched silicon wafer manufactured by International SEMATECH (ISMT) and characterized at National Institute of Science and Technology (NIST). The advantages of this wafer are its well known topography and its suite of different metrology targets. A good fit to both analytical and experimental results is demonstrated, attesting to the capabilities of our enhanced simulation platform. The results for both the analytical and experimental validations are presented.

As the dimensions of devices shrink and the processing of new devices gets more complex, the requirements for overlay are becoming tighter. Many process elements and previously unmodeled components now dominate the total overlay budget; such as reticle error, alignment-mark quality and design, tool control, alignment system setup and alignment sampling layout, etc. Unmodeled errors (RMSE) consume a larger percentage of the total overlay as the tolerances become tighter. The strategy pursued was to reduce the contribution of each of these elements to as small as possible. In this paper, an improved sampling method is introduced to optimize the sampling layouts in order to minimize RMSE in alignment modeling solutions. The applications of these optimized sampling layouts in both production and system maintenance are also introduced.

This paper studies the alignment performance of dual damascene patterning using two different integration schemes. These schemes cater to two different low K materials. The via first scheme is used for CVD type material while the dual hardmask trench first is used for spin on low K material. The alignment and exposure is performed on Nikon scanner S203B using LSA (Laser Step Alignment; a scattering based system) and FIA (Field Interferometer Alignment; a contrast-based system) systems while the overlay is measured on KLA 5200XP. Many different mark designs were evaluated for both the schemes. The effect of resist coat was found to be different on different mark types. Difference was also seen in the signal strengths in X and Y directions. Process optimisation for scanner was done by varying the slice level, signal processing algorithms, and focus. The initial alignment mark evaluations were done by studying the signals obtained from such marks and comparison of Static Random Factor (SRF) and Dynamic Random Factor (DRF) obtained from the scanner. The best marks were then applied to the lot splits and the final performance was evaluated by measuring the total overlay results. Results showed that SRF and DRF evaluation could be used for screening to find out the best marks for a certain level. It can also be concluded that dual damascene alignment is possible with trench first scheme that has small step height using the LSA window mark or the FIA narrow island mark. For both schemes the best performer was the FIA Narrow Island Mark. Hence it can be concluded that better alignment performance could be obtained by special alignment mark designs for a specific level.

Critical dimensions in current and next generation devices are driving the need for tighter overlay registration tolerances and improved overlay metrology tool accuracy and repeatability. Tool matching, performance evaluation, and a move towards closed-loop image placement control all place an increase on the importance of improved accuracy and calibration methodology. In response to these industry needs, the National Institute of Standards and Technology (NIST) is introducing a calibrated overlay wafer standard. There are, however, a number of calibration requirements, which must be addressed when using these standards. These include identification of the best methods for evaluating uncertainties when using traceable, calibration artifacts, proper data acquisition and analysis, and the best calibration strategy.

Generally, the potential impact of systematical overlay errors on 300mm wafers is much larger than on 200mm wafers. Process problems which are merely identified as minor edge yield detractors on 200mm wafers, can evolve as major roadblocks for 300mm lithography. Therefore, it is commonly believed that achieving product overlay specifications on 300mm wafers is much more difficult than on 200mm wafers. Based on recent results on high volume 300mm DRAM manufacturing, it is shown that in reality this assumption does not hold. By optimizing the process, overlay results can be achieved which are comparable to the 200mm reference process. However, the influence of non-lithographic processes on the overlay performance becomes much more critical. Based on examples for specific overlay signatures, the influence of several processes on the overlay characteristics of 300mm wafers is demonstrated. Thus, process setup and process changes need to be analyzed monitored much more carefully. Any process variations affecting wafer related overlay have to be observed carefully. Fast reaction times are critical to avoid major yield loss. As the semiconductor industry converts to 300mm technology, lithographers have to focus more than ever on process integration aspects.

The ability of a critical dimension scanning electron microscope (CD-SEM) to resolve differences in the widths of two lines is determined by measurement repeatability and any sample-dependent biases. In order to ascertain the dependence of these quantities upon eight different parameters specifying the sample geometry, instrument conditions, and noise, the MONSEL Monte Carlo electron simulator has been used to calculate secondary electron images for varying depth of focus, sample edge shape, electron beam spot size, and proximity of neighboring lines. To each of these imaegs was added noise with varying total power but with that power distributed across spatial freqencies so as to match the shape of the power spectral density measured in one or the other of two different commercial CD-SEMs in a fabrication facility environment. The edge positions from these simulated noisy images were then 'measured' as would be done in a CD-SEM, employing both commonly used and experimental edge location algorithms. Simulations were performed for 14,400 different combinations of values for the eight parameters. From many repetitions of noise, the repeatability of such edge measurements was ascertained for each of these. Since in a simulation the true edge positions are known, the biases of these edge determinations were also determined. The noise amplitude, choice of edge detection algorithm, and beam size are significant factors in measurement repeatability. The CD-SEMs measurement repeatability may be an order of magnitude better than its spatial resolution. For some edge detection methods the bias is a function of edge shape. This means that in a manufacturing environment in which the shape varies, there will be a random component of error that is not captured in the usual same-sample tests of instrument precision.

International SEMATECH (ISMT) and the National Institute of Standards and Technology (NIST) are working together to improve the traceability of atomic force microscope (AFM) dimensional metrology in semiconductor manufacturing. The rapid pace of technological change in the semiconductor industry makes the timely introduction of relevant standards challenging. As a result, the link between the realization of the SI (Systeme International d’Unites, or International System of Units) unit of length - the meter - and measurements on the fab line is not always maintained. To improve this situation, we are using an at-line critical dimension-AFM (CD-AFM) at ISMT as a developmental platform. This tool has been implemented as a Reference Measurement System (RMS) in the facilities at ISMT. However, it is currently being replaced by a next-generation CD-AFM tool. Using the current tool, we have performed measurements needed to establish the traceability chain and developed uncertainty budgets. Specifically, we have developed uncertainty budgets for pitch, height, and critical dimension (CD) measurements. Some evaluations were performed using samples for which a full traceability chain is not available. We expect to improve the uncertainties further for such samples. At present, the standard uncertainties are estimated to be approximately 0.2 % for pitch measurements, 0.4 % for step height measurements, and 5 nm for CD measurements in the sub-micrometer range. Similar budgets will be developed for the new tool once it is installed. We will describe our methodology for RMS implementation and the major applications for which it has been used. These include measurements on new NIST/ISMT linewidth standards, a reference tool for CD-scanning electron microscopes (SEMs), metrology on photo-masks, CD-SEM benchmarking, and 193 nm resist shrinkage measurements.

Three parameters, measurement times, charging distances, and charging area, are studied with respect to measurement of the local charging effect. We found that the effects of measurement times and charging distances to the local charging is under observation limit and the measured CD deviation is very small. However, the charging area is found to be the most dominant parameter for local charging. A 7-nm CD deviation from this local charging is observed. After the root cause of the local charging is understood and controlled, we use an extra charging area at the opposite side of the measurement site to compensate for the charging effect. The SEM image and CD deviation are greatly improved after this compensation. At last, a novel measurement algorithm is introduced to deal wiht the actual OPE evaluation. From simulation, the net Coulomb force experienced during the measurement is greatly reduced with the new algorithm compared with that used in the normal measurement sequence. The comparison of the global charging and local charging effects is also discussed in this report.

The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. Aggressive model-based OPC and Phase Shift Mask technology are being used more and more frequently in order to achieve the extremely tight mask CD specifications required by 90nm technology node. State-of-the-art mask inspection is challenged to detect CD defects close to metrology resolution. Inspection of OPC and PSM masks is critical; OPC feature dimensions are usually near or below the resolution limits of mask exposure. In addition, chrome defects can be semitransparent and change the intensity of light on the wafer. In this paper aerial-image based mask inspection is investigated and presented. The concept inspects a given mask based on its aerial image with selected wafer exposure conditions, thus 'finds only defect which will print'. This paradigm shift in mask inspection philosophy provides the unique opportunities of verifying and controlling the entire aerial image generated by the inspected mask. As reticle enhancement techniques like OPC and EAPSM are designed to enhance the aerial image of a mask, this concept offers a comprehensive way of inspecting these techniques. The focus of the inspection is shifted from detecting every single minor change on mask to detecting what on mask could possibly impact the printing image quality on the wafer. The focus of the paper is to analyze the impact of different exposure and lithography process conditions onto the inspection sensitivity. The standard defect sensitivity and runability test mask UIS10 and other advanced real production masks were printed under different exposure and process conditions resembling production-worthy 193nm lithography processes. The masks then were inspected using Etec's aerial image-based inspection concept. Detection sensitivities and CD variations on the wafer are analyzed and compared.

A method that uses Fourier Transform Infrared (FTIR) Reflectance spectroscopy to determine the depths of poly silicon filled trenches is described. These trenches, which form the cells for trench DRAM, are arranged in arrays that are periodic in both directions. The method is non-contact and non-destructive. Large number of points per wafer can be easily measured to determine etch uniformity performance. Unlike cross section SEM based metrology, the wafer does not need to be cleaved, and thereby destroyed. The technique is thus suited for in-line metrology of product wafers. The FTIR technique was found t be very robust and provided excellent correlations with SEMs have been observed for 110 nm trenches and are reported in the paper. The method is a viable manufacturing solution for inline, non-destructive, rapid metrology on product wafers.

The challenges facing current dimensional metrologies based on scanning electron microscopy (SEM), atomic force microscopy (AFM), and light scatterometry for technology nodes of 157 nm imaging and beyond may require the development of new metrologies. We provide results of initial tests of a measurement technique based on Small Angle X-ray Scattering (SAXS) capable of rapid measurements of test samples produced using conventional test masks without significant sample preparation. Using a sample photoresist grating, the technique is shown to apply to both organic, including photoresist, and inorganic patterns, including metal and oxide. The sub-Angstrom wavelength provides nanometer level resolution, with significant room for increased resolution. SAXS provides a dramatic improvement over the use of small angle neutron scattering (SANS) in measurement resolution. An additional advantage is the potential of developing a SAXS-based metrology tool on a laboratory scale.

A spectroscopic, diffraction based technique is proposed in this paper as an alternative solution for overlay metrology in technology nodes below 90 nanometers. This novel technique extracts alignment error from broadband diffraction efficiency of specially designed diffraction targets in real-time. Feasibility of the technique is studied for a front-end process flow by measuring grating targets printed on a series of wafers which were intentionally mis-processed to introduce inter-die (grid) level programmed overlay errors. Correlation to conventional imaging overlay measurements is demonstrated. Short term and long term data sets demonstrate sub-half-nanometer in 3-sigma statistical parameters that characterize the diffraction overlay system, repeatability, reproducibility, Tool-Induced-Shift and tool-to-tool matching. The resulting total measurement uncertainty for this technique is thus demonstrated to be in the sub-nanometer range.

In this article are demonstrated the nanoscale capabilities of scatterometry, an optical metrology technique for the determination of the grating parameters. Notably, for both ellipsometric-scatterometry and phase-moudlation scatterometry we are now currently using shorter wavelength laser soruces, namely 325 nm in UV. We added to the scatterometer the ability to perform Φ-scanning measurements. This capability adds new degrees of freedom to the sensitivity optimization procedure. Because the sensitivity analysis formalism leads us to the conclusion that sensitivity is provided mainly be anomalies, a rigorous analysis of a certain type of anomaly, the most likely to occur for our type of samples, was made using Modal Analysis. Our analysis allows for the prediction of the anomaly position. This procedure allows us to find the optimum measurement configuration much faster than the SAF formalism used in the past.

The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps, to back-end-of-line device parametric test results, enables semiconductor manufacturers to minimize the cost per good die produced, by accurately screening out-of-spec product early in the process flow. The significant increase in the number of chips on today's 300mm wafers heightens the importance of obtaining reliable in-line data. In addition, the reduction of design rules to 130nm and below is driving precision requirements on metrology to <1nm, in order to maintain acceptable precision-to-tolerance (P/T) ratios. Historical methods of in-line metrology (Low Voltage Scanning Electron Microscopy, Atomic Force Microscopy, Electrical Critical Dimension Measurement) all face limitations with regards to precision, correlation, or throughput. This paper will demonstrate the use of Spectroscopic Ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique is currently being utilized for in-line process control and product disposition, at the gate lithography and etch process steps, on 130nm generation logic devices manufactured in Texas Instruments' DMOS 6 300mm wafer fabrication facility. A brief description of the measurement theory and gate profile measurement solution for both dense and isolated structures will be given. This will be followed by data generated from DMOS 6 production material. Using Spectroscopic Ellipsometry, precision results of <0.5nm for CD and height, and <0.25 degrees for profile sidewall angle were obtained at both the lithography and etch measurement steps. The use of CD and sidewall angle information in an APC loop to improve control over the gate trim etch process will also be discussed. Data will be presented showing univariate and multivariate correlation of gate etch profile parameters to post-metalization transistor drive current (IDrive) that is equivalent or superior to existing metrology techniques. Finally, examples of where Spectroscopic Ellipsometry has both increased sensitivity and shortened response time to gate etch process excursions will be presented.

Scatterometry is a contender for various measurement applications where structure widths and heights can be significantly smaller than 70 nm within one or two ITRS generations. For example, feedforward process control in the post-lithography transistor gate formation is being actively pursued by a number of RIE tool manufacturers. Several commercial forms of scatterometry are available or under development which promise to provide satisfactory performance in this regime. Scatterometry, as commercially practiced today, involves analyzing the zeroth order reflected light from a grating of lines. Normal incidence spectroscopic reflectometry, 2-theta fixed-wavelength ellipsometry, and spectroscopic ellipsometry are among the optical techniques, while library based spectra matching and realtime regression are among the analysis techniques. All these commercial forms will find accurate and precise measurement a challenge when the material constituting the critical structure approaches a very small volume. Equally challenging is executing an evaluation methodology that first determines the true properties (critical dimensions and materials) of semiconductor wafer artifacts and then compares measurement performance of several scatterometers. How well do scatterometers track process induced changes in bottom CD and sidewall profile? This paper introduces a general 3D metrology assessment methodology and reports upon work involving sub-70 nm structures and several scatterometers. The methodology combines results from multiple metrologies (CD-SEM, CD-AFM, TEM, and XSEM) to form a Reference Measurement System (RMS). The methodology determines how well the scatterometry measurement tracks critical structure changes even in the presence of other noncritical changes that take place at the same time; these are key components of accuracy. Because the assessment rewards scatterometers that measure with good precision (reproducibility) and good accuracy, the most precise scatterometer is not necessarily the best.

We have developed in-line dose and focus monitoring techniques for the detailed analysis of critical dimension error and accurate process control. From exposed wafers, effective does and focus are measured with specificed monitor marks built on a reticle. The contributions of effective dose and focus to critical dimension error on device chips were clarified in a fabrication proces of 110 nm isolated pattern with a KrF scanner. The critical dimensions error was described as a function of effective dose and focus, which include various process fluctuations. We could determine whether current exposure settings such as dose input and focus input were adequate or not. Based on the experimental data, we estimated the benefit of simultaneous Run-to-Run control of dose and focus. The estimation clarifies that it realizes total critical dimension control including Run-to-Run and intra-Run.

As the design rules shrink below 130nm it will become increasingly important to monitor and control focus and dose in-line, on product wafers to maintain the ever-decreasing process window. On process layers today, it is not uncommon to see focus related errors equaling between 50-100nm in magnitude. Today these errors go undetected and CD changes are typically corrected by making a dose correction to the exposure tool. However, corrections using dose can lead to significantly smaller process latitude and therefore, products out of spec. Using a technique that was first developed by Christopher Ausschnitt at IBM Microelectronics it is possible to monitor focus and dose on production layers with a single compact target. Extending this technology on an advanced optical tool allows for precise measurements of focus and dose errors. This paper will describe the methodology of inline focus and dose monitoring using this technique on 130nm process technology with an outlook on the expectations for future nodes. Results, including focus and dose sensitivity from multiple process steps on production wafers will be shown.

New metrology capabilities available on a state-of-the-art CD-SEM system are discused that allow quantification of contact and via profiles directly after lithography processing. The so-called Profile Grade (PG) analysis capability is based on secondary electron emission information obtained while scanning the contact or via holes. Three PG ranges can be distinguished to quantify contact profile quality; 0 < PG < 1.4 for closed contacts, 1.4 < PG < 1.7 for semi-opened contacts, and 1.7 < PG < 5 for fully opened contacts. These ranges are independent of resist type. The PG analysis is shown to be more accurate and sensitive in predicting contact profile marginality than classical CD measurements. A common practice in lithography processing is to use overexposure conditions to built in a safety margin ensuring that contacts are fully opened. The present work demonstrates that monitoring the lithography process by using the PG profile analysis with a lower spect limit in addition to the classical CD measurement enables the use of a lower exposure dose which increases stepper throughput. In addition, risk to yield loss is decreased because the quality of the contacts in the lower CD range can be quantified by using the PG profile analysis methodology.

Using scatterometry based on Spectroscopic Ellipsometry, a complete study of Gate lithography level measurement on standard products has been conducted. Experiments were done on typical ST batches for 120, 90, and 65 nm nodes. KLA-Tencor SpectraCD SE system is used to collect and analyze line critical dimensions and profiles. A systematic correlation with Scanning Electron Microscope (SEM) is done, completed by a cross section analysis. The study also takes into account lithography defect anlysis using a specific targets with intentionally generated process failures. Our objective is to determine the sensitivity window of such measurment technique to process defect and marginal process conditions. We show that KLA-Tencor SpectraCD allows a full reconstruction of the line profile - as well as the film stack underneath it - with values that are in agreement with production control. Cpm values obtained on products demonstrate that SE based scatterometry fulfils all requirements to be integrated in a production envrionemnt and provides suitable metrology for advanced lithography process monitoring.

In the production of sub 140nm electronic devices, CD metrology is becoming more critical due to the increased demands placed on process control. CD metrology using CD-SEM is approaching its limits especially with respect to precision, resolution and depth of field. Potentially, scatterometry can measure structures down to 50nm with the appropriate precision. Additionally, as scatterometry is a model based technique it allows a full reconstruction of the line profile and the film stack. In this work we use SE based scatterometry in the control of a 110nm DRAM WSix Gate process at the Litho and the Mask Open step. We demonstrate the use of a single trapezoid as a basic shape model in FEM and field mapping applications as well as in a high volume production test. The scatterometry results are compared to CD-SEM data. We show that for the GC Litho application, n&k variations in some of the stack materials do not affect the scatterometry CD measurement significantly.

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. INTERNATIONAL SE-MATECH has been leading and supporting efforts to investigate the impact of the tech-nology introduction. This paper examines the issue of manufacturing tolerances available for image placement on adjacent critical levels (overlay) at the 90nm and 65nm technol-ogy nodes. The allowable values from the 2001 release of the ITRS Roadmap are 32nm for the 90nm node, and 23nm for the 65nm node. Even the 130nm node has overlay requirements of only 46nm. Employing tolerances that can be predicted, the impact of existing production/processing tolerance accumulation can provide an indication of the challenges facing the manufacturer in the production of 90nm and 65nm Node devices.

Phase defects in extreme UV lithography masks made from Mo/Si multilayer thin films can be removed by heating the metal multilayer to produce a localized phase transition. The experimental situation has been simulated using a Monte Carlo method to determine the deposition of energy from the incident electrons, and the resultant elevation of temperature has been found by solving the thermal diffusion equation. The effects of operating parameters such as beam energy, beam current, and beam spot size have been investigated. It is shown that the effect of surface radiation cooling is negligible, and that only a steady state solution needs to be considered.

Sub-wavelength lithography used for today's 130nm and 90nm node devices requires new approaches to both lithography processes and chip design. Reticle complexity has increased as OPC and Phase Shift techniques are used to improve lithography process windows at smaller design rules. Among new revolutionary design implementations specifically for metal layers, the X Architecture is an interconnect architecture based on the pervasive use of diagonal wiring, reducing total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, and cost. An important consideration for implementation of any new IC manufacturing process is early verification that the new process, technology, or design is has stable manufacturability in a production environment. To perform this verification for X Architecture reticle inspectability, an investigation was launched with the goal to optimize reticle inspection for X Architecture metal layers. The TeraStar reticle inspection system was used inspect two sources of X Architecture metal 4 and metal 5 layers, both employing X Architecture design data. This paper will present the results of these reticle inspections and will report the overall inspectability of the X Architecture design and the viability of TeraStar reticle inspection on these reticles in a production environment.

Binary and phase-shifting chromium on quartz optical photomasks have been successfully investigated with high-pressure/environmental scanning electron microscopy. The successful application of this methodology to semiconductor photomask metrology is new because of the recent availability of a high-pressure SEM instrumentation equipped with high-resolution, high-signal, field emission technology in conjunction with large chamber and sample transfer capabilities. The high-pressure SEM methodology employs a gaseous environment to help diminish the charge build-up that occurs under irradiation with the electron beam. Although very desirable for the charge reduction, this methodology has not been employed much in photomask or wafer metrology until now. This is a new application of this technology to this area, and it shows great promise in the inspection, imaging and metrology of photomasks in a charge-free operational mode. This methodology also holds the potential of similar implications for wafer metrology. For accurate metrology, high-pressure SEM methodology also affords a path that minimizes, if not eliminates, the need for charge modeling. This paper presents some new results in high-pressure SEM metrology of photomasks.

It is well known that shrinking k1 factors are making via and contact layers more difficult to print with acceptable latitude and low defectivity. A typical method for improving the common process window is to use embedded attenuated phase shifting masks (EAPSM). However, even with the improved resolution offered by this technology, small deviations in reticle contact size are producing increasingly severe patterning problems - at the extreme, missing contacts. In this study, we conducted an investigation of a production reticle causing repeating wafer defects that passed the reticle manufacturer’s outgoing inspection. We have examined this reticle using a new inspection algorithm that measures reticle contact energy. This technique successfully detected slightly undersized contacts directly corresponding to the coordinates of the repeating wafer defects. However, the reticle contact energy inspection also detected numerous undersized contacts that were not detected by wafer SEM inspection. We have produced and printed to wafer a test reticle with programmed over and under sized contacts in order to create a new reticle specification to detect defective contacts before they are shipped to the wafer fab.

NIST is preparing to issue the next generation in its line of binary photomask linewidth standards. Called SRM 2059, it was developed for calibrating microscopes used to measure linewidths on photomasks, and consists of antireflecting chrome line and space patterns on a 6 inch quartz substrate. Certified line- and space-widths range from nominal 0.250 μm to 32 μm, and pitches from 0.5 μm to 250 μm, and are traceable to the definition of the meter. NIST's reference value, the definition of the meter, is well defined and unconditionally stable. Any replacement or duplicate NIST linewidth standard will be traceable to this same reference, and thus traceable to any other NIST length standard. Establishing such traceability requires evaluation of the effects of all error sources affecting the calibrations. While the meter (and the μm) are well-defined, the geometrical width of a chrome line with nonrectangular cross section is not, and so the 'true value' linewidth must be carefully defined to best meet users' needs. The NIST linewidth measurement system and the optical imaging model used have both been updated for this SRM. Remeasurements of previous NIST SRMs 473 and 475 reveal discrepancies which are difficult to reconcile with previous international comparisons between NIST, NPL, and PTB.

Control of critical dimension (CD) variation is of extreme importance in modern semiconductor manufacturing processes. To be controlled, the nature of CD variation must be understood. This paper outlines a method for characterizing systematic spatial variation by means of dense electrical linewidth measurements, including actual sample data. In addition, since exhaustive sampling is prohibitively expensive for routine use, a method is discussed for finding an optimum economical sampling plan and using this plan to track systematic CD variation over time.

Due to the rapidly reduced imaging process windows and increasingly stingent device overlay requirements, sub-130 nm lithography processes are more severely impacted than ever by systamic fault. Limits on critical dimensions (CD) and overlay capability further challenge the operational effectiveness of a mix-and-match environment using multiple lithography tools, as such mode additionally consumes the available error budgets. Therefore, a focus on advanced process control (APC) methodologies is key to gaining control in the lithographic modules for critical device levels, which in turn translates to accelerated yield learning, achieving time-to-market lead, and ultimately a higher return on investment. This paper describes the implementation and unique challenges of a closed-loop CD and overlay control solution in high voume manufacturing of leading edge devices. A particular emphasis has been placed on developing a flexible APC application capable of managing a wide range of control aspects such as process and tool drifts, single and multiple lot excursions, referential overlay control, 'special lot' handling, advanced model hierarchy, and automatic model seeding. Specific integration cases, including the multiple-reticle complementary phase shift lithography process, are discussed. A continuous improvement in the overlay and CD Cpk performance as well as the rework rate has been observed through the implementation of this system, and the results are studied.

Overlay specifications are getting tighter and lithographic processes come close to their limits. Minimal process changes can lead occasionally to overlay excursions. We explore the use of advanced query and multivariate analysis techniques to address overlay issues in an advanced production environment. We demonstrate the use of advanced query and multivariate analysis techniques in 4 case studies: identifying problem overlay recipes, comparing sources of variation in backend processing, identifying lithography tool issues, and overlay tool monitoring. Due to the large number of possible filter combinations several simple queries were used as starting points in order to explore the existing overlay database in a systematic way. The goal of the systematic evaluation of the available information was to find the most efficient methods to analyze and identify specific overlay problems. During this screening process, device, layer, and exposure tool specific metrics were found. For the most important findings the data filtering was refined in a second stage. Additional sources of information were incorporated for verification and to make correct conclusions. Standardized sets of queries can be used to monitor the lithographic process or to quickly pin point the root causes. It is shown that one can efficiently identify process, tool, and metrology sources of variation.

One goal of CD metrology is to monitor lithographic process control and how it relates to post-etch results. At present, in-fab process control for this purpose is achieved through top-down CD measurements. To acquire profile information requires destructive cross-section SEM measurements or time-consuming AFM measurements. To find height and profile information about a resist or etched structure directly on a CD-SEM, techniques using the combination of in-column beam tilt and stereographic imaging have been developed, implemented and improved on the Applied Materials NanoSEM-3D. This work is an extension of results previously published, although the tool used is greatly improved and the target feature stacks more thorough. The column of the NanoSEM-3D is designed to be able to electronically tilt the incident beam at small angles as it approaches the sample, through bending the beam within the column. Two images can be captured of the sidewall of the feature target, one at a smaller tilt angle and one at a larger tilt angle. Through matching common features between these two images, a reconstructed profile can be mathematically generated. A feature height and sidewall angle can be calculated, and general shape information such as top-rounding, footing and undercutting can also be displayed. To benchmark the effectiveness of this new technique, an experiment has been conducted to quantify the repeatability and reproducibility of height and sidewall angle measurements of lines of resist-on-poly and the resulting etched-poly lines, and correlate these to measurements of the these same profiles using XSEM to determine the accuracy of the technique. This study will span a reasonable lithographic process window. We hope to demonstrate the necessary precision and accuracy capability to non-destructively replace some cross-section work. In applying these techniques to a common etch bias problem, we also hope to demonstrate a strong correlation which can be used to directly predict post-etch behavior and serve as a model for other etch processes, work with which XSEM cross-sections have typically been used until now. The profile measurement technique is also applied to other CMOS features such as etched STI trench, resist and etched contact holes, and resist and etched damascene trenches and vias, with calculated tool precisions for feature height and sidewall angle.

The paper introduces an improved, physics-based function for fitting lithographic data from focus-exposure matrices. Unlike simple polynomial functions, the coefficients of this equation offer physical insight into the meaning and nature of the data. Derivation of this equation from first principles of the physics of lithographic imaging is presented. Examples based on typical experimental data are shown and the advantages of using a physics-based fitting function is described based on improved fitting and noise filtering.

In this work, CD control issue at 0.37 K1 optical lithography will be discussed in terms of lens aberration sensitivity. Specific aberration terms that affect CD asymmetry on isolation, word line and storage node layers were investigated by simulation and CD uniformity measurement. The lens aberration was characterized by LITEL ISI (In-Situ Interferometer) and the aberration sensitivity was investigated by Solid-C aerial image simulation. From this result, we can understand the relation between some significant Zernike terms and CD control of DRAM’s critical layers.

Due to its low resistance and high electromigration performance, copper is now considered as a better metalization than the currently used aluminum based alloys. Dual damascene architecture is generally proposed for fabrication of multilevel copper interconnection. However, in the case of via first dual damascene scheme, we have great difficulties in M2 Trench photoprocess such as alignments and overlay measurements because this scheme makes too high topography of via patterns. Alignment marks and overlay targets made during via patterning process do not have good image contrasts after coating BARC and photoresist. Deteriorated image contrast of alignment marks and overlay targets increases the uncertainty in the alignment and overlay measurement. The image contrasts of alignment mark become worse after coating BARC and photoresist, resulting in weak, noisy, and asymmetric alignment signals. In this paper, we evaluated the impacts of mark structure, geometry, and BARC processing for the alignments and the overlay measurements using convex or concave structures, bar or slit structures, and special designed structures in M2 trench photo process. We also investigated the copper filled keys on M1 trench layer as alternative alignment targets.

New methods to enhance and improve algorithm performance and data analysis are being developed at NIST for overlay measurement applications. Both experimental data and improved theoretical optical scattering models have been used for the study. We have identified error sources that arise from (i) the optical cross talk between neighboring lines on an overlay target (ii) the selection of the window size used in the auto-correlation and (iii) the portion of the intensity profile that is used in the overlay calculation (defined as a truncated profile). Further, we suggest methods to optimally minimize these error sources. We also present a relationship between tool-induced shift (TIS) and the asymmetry in the intensity profile.

In this publication we introduce a new metric for process robustness of overlay metrology in microelectronic manufacturing. By straightforward statistical analysis of overlay metrology measurements on an array of adjacent, nominally identical overlay targets the Overlay Mark Fidelity (OMF) can be estimated. We present the results of such measurements and analysis on various marks, which were patterned using a DUV scanner. The same reticle set was used to pattern wafers on different process layers and process conditions. By appropriate statistical analysis, the breakdown of the total OMF into a reticle-induced OMF component and a process induced OMF component was facilitated. We compare the OMF of traditional box-in-box overlay marks with that of new gratingbased overlay marks and show that in all cases the grating marks are superior. The reticle related OMF showed an improvement of 30 % when using the new grating-based overlay mark. Furthermore, in a series of wafers run through an STI-process with different Chemical Mechanical Polish (CMP) times, the random component of the OMF of the new grating-based overlay mark was observed to be 40% lower and 50% less sensitive to process variation compared with Box in Box marks. These two observations are interpreted as improved process robustness of the grating mark over box in box, specifically in terms of reduced site by site variations and reduced wafer to wafer variations as process conditions change over time. Overlay Mark Fidelity, as defined in this publication, is a source of overlay metrology uncertainty, which is statistically independent of the standard error contributors, i.e. precision, TIS variability, and tool to tool matching. Current overlay metrology budgeting practices do not take this into consideration when calculating total measurement uncertainty (TMU). It is proposed that this be reconsidered, given the tightness of overlay and overlay metrology budgets at the 70 nm design rule node and below.

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

Progress in photolithograpy depends upon the availability of photoresists capable of printing increasingly fine features. New resist materials are constantly in demand, for instance to enable the use of sources and optics operating at shorter wavelengths. For the development of new resists, it is very valuable to have a quantitative metric for the spatial resolution of the photoresist itself. The spatial resolution of an imaging optical system is generally described by a line spread function or, equivalently by its Fourier transform, the modulation transfer function. We apply the formalism of a line spread function to the photoresist film and show that given a model for the development process, which transforms the continuous-valued latent image to a binary-valued relief profile, the modulation transfer function can be deduced from measurements of linewidth vs. dose for sinusoidal exposures made by 2-beam interferometric lithography. An important advantage of the interferometric technique is that it does not require highly optimized, and thus expensive, optics for the wavelength under investigation. This methodology has been applied to commercial and experimental photoresist materials. As an example, the experimental results show that the line spread function of the deep-UV resist UVII-HS has a full width at half maximum of approximately 50 nm.

Coumarin 6 (C6), a pH sensitive fluorescent molecule were doped into commercial resist systems to demonstrate a cost-effective fluorescence microscopy technique for detecting latent photoacid images in exposed chemically amplified resist films. The fluorescenec image contrast is optimized by carefully selecting optical filters to match the spectroscopic properties of C6 in the resist matrices. We demonstrate the potential of this technique for two sepcific non-invasive applications. First, a fast, conventient, fluorescence technique is demonstrated for determination of quantum yeidsl of photo-acid generation. Since the Ka of C6 in the 193nm resist system lies wihtin the range of acid concentrations that can be photogenerated, we have used this technique to evaluate the acid generation efficiency of various photo-acid generators (PAGs). The technique is based on doping the resist formulations containing the candidate PAGs with C6, coating one wafer per PAG, patterning the wafer with a dose ramp and spectroscopically imaging the wafers. The fluorescence of each pattern in the dose ramp is measured as a single image and analyzed with the optical titration model. Second, a nondestructive in-line diagnostic technique is developed for the focus calibration and validation of a projection lithography system. Our experimental results show excellent correlation between the fluorescence images and scanning electron microscope analysis of developed features. This technique has successfully been applied in both deep UV resists e.g., Shipley UVIIHS resist and 193 nm resists e.g., Shipley Vema-type resist. This method of focus calibration has also been extended to samples with feature sizes below the diffraction limit where the pitch between adjacent features is on the order of 300 nm. Image capture, data analysis, and focus latitude verification are all computer controlled from a single hardware/software platform. Typical focus calibration curves can be obtained within several minutes.

Resist slimming under electron beam exposure introduces significant measurement uncertainty in the metrology of 193 nm resists. Total critical dimension (CD) uncertainty of up to 10 nm can arise from line slimming through a combination of the line slimming during the initial measurement pass and the variation of line slimming across the wafer. For a 100 nm process, the entire CD error budget, can be consumed by line slimming. This research examines the uncertainty that results from the use of offset techniques to account for resist slimming in the process control of 193 nm resist CDs. The uncertainty associated with such offset techniques can be as great as 10 nm, depending upon the 193 nm resist and landing energy evaluated. Data are presented to demonstrate that 193 nm resist CD features experience line slimming greater than 5 nm at 500 eV landing energy during the initial measurement pass. Further, subsequent measurements demonstrate greatly reduced slimming and as a result are not indicative of the true magnitude of line slimming. Experiments conducted using CD-AFM pre- and post-analysis, demonstrate that ultra low landing energies significantly decrease the line slimming, reducing it to 1 nm or less.

Carbon nanotubes (CNT) have exceptional mechanical strength at small diameters needed for measuring high aspect ratio features. Manually attached carbon nanotube atomic force microscopy probes have demonstrated exceptional longevity. Unfortunately, due to the manual attachment process, and the usually arbitrary diameter and length of the used CNT, such probes are not suitable for high aspect ratio critical dimension metrology (CDM). For reproducible and accurate CDM measurements precisely defined CNT probes are necessary. We are reporting about the progress made growing carbon nanotubes (CNT) directly on top of standard Si probes. The goal is to produce well-defined long lasting probes for CDM measurements in the <100 nm pitch range. Our efforts currently focus on manufacturing precisely aligned CNT having defined locations, diameters and lengths. This is accomplished by using plasma assisted chemical vapor deposition in combination with focused ion beam (FIB) patterned catalyst films. Our results demonstrate that it is possible to manufacture 1:10 aspect ratio CNT probes at <100 nm diameters.

Real-time optical CD metrology(1), employing fast numerical solutions to the diffraction of light from microelectronic features, is beginning to gain wide usage for sub-130nm IC processing. Applications of this method heretofore have concentrated on two steps in the patterning process: the 'develop inspect' (DI) step, at which point the pattern features are formed in the photoresist but prior to etch, and the 'final inspect' (FI) step, after the etch process has transferred the feature into the underlying IC layer(s). In this article, we examine another application: use of optical CD metrology for rapid characterization of stepper/scanner performance and optimization. In order to be useful to characterize a litho process, we found it necessary to expand the set of fitting parameters to include the pitch of the measured line/space array. This is due to two practical matters: first, the pitch imprinted on a wafer is the result of the pitch on reticle and second, the pitch on the wafer is a result of imaging magnification. As a result, this parameter can vary by several percent typically, for a pitch target of 240 to 350nm. Without taking this parameter into account, high-quality fitting of results over a full-field focus-exposure matrix (FEM) wafer, for example, is problematic. With the pitch included as a fitting parameter, it is possible to obtain excellent data-model fits across an entire FEM with a single metrology recipe.

The production of state-of-the-art integrated circuits requires better dimensional metrology than is currently available. The reliance on precision alone will not deliver the needed, close to atomic level performance. Without thorough analysis of the accuracy and precision performance of the metrology tools it is impossible to fulfill the requirements dimensional metrology has to meet. WIth the implementation and use of the existing, internationally accepted and recommended guidelines for evaluating and expressing the results and uncertaintly of measurements these problems can be minimized and ultimately overcome. These guidelines spell out the proper way of dealign with measurment results and their use will uncover substantial hidden problems that hold back the performance of current metrology tools. Possibilities for further improvements will also present themselves. This paper describes the present and preferred way of handling dimensional measurement results for integrated circuit technology and gives a detailed list of possible errors and sources measurement inaccuracy and uncertainty found in scanning electron microscopes.

Measurement using electron beam tilt has recently been highlighted as holding the promise of future sidewall angle and thickness determinations in the CD SEM in a manufacturing environment. But even before robust tilted beam measurements can be made, a thorough understanding of stray tilt, its characterization and control, is needed to provide the foundation for tilt calibrations and measurements. Stray tilt is the amount of unintended angular deviation of the electron beam from the normal to the specimen's (wafer) surface. Stray tilt is common to all SEMs used in manufacturing due to the following contributors: mechanical tolerances, acting both within the SEM column and between the SEM column and the chamber and the sample holder; and also residual and parasitic magnetic and electrostatic fields - these fields are generated both within and outside of the SEM integrated stand-alone unit. Past characterization attempts addressed this issue through an asymmetry specification. Recent data has suggested that stray tilt errors can have significant negative effects on today's critical dimension measurements, especially on a fleet of CD SEM tools with different amounts of stray tilt. This paper explores the measurement, monitoring and minimizing of stray tilt and the consequences on tool matching.

Atomic Force Microscopy (AFM), a modality of SPM, has been used for capturing metrological data of a wide range of surface types, with possible nanometer range resolution. However, AFM images of high aspect ratio surface features such as lines, steps or sharp or sharp edges, are commonly distorted by convolution, which reduces metrological accuracy and data repeatability. In order to mitigate these limiting factors, we developed and implemented a novel AFM imaging mode and image deconvolution procedure that utilizes the principle of geometric reconstruction by stereo imaging. In this scheme, we combine multiple images of a sample, taken at different angles, allowing for the separation of convolution artifacts form true topographic data. The method is iteraive from an algorithmic standpoint and converges to a geometric reconstruction of the sample with minimal uncertainty. Most importantly, this technique does not require a priori probe characterization. It also reduces the need for slender or sharper probes, which are more prone to wear and damage, leading to loss of system reliability. In this paper, we briefly cover the fundamentals of the method and proceed to analyze validation result obtained via both simulation and experimentation. Resulting reconstructions obtained with this novel AFM stereo imaging approach are directly compared to white light interferometer and SEM data.

Semiconductor device manufacturing demands rapid ramp of yield together with feature size reduction, especially for logic and ASIC because of their short-lives and small volume production characteristics. As a technological breakthrough for rapid yield ramp of such devices, we have endeavored to integrate CAD technology with SEM for printed pattern observation, and have developed Grade Scope, an evaluation technology, by combining the wafer proces and upstream design process.

Specular-mode spectroscopic ellipsometry (SE) or reflectometry (SR) from periodic gratings have been successfully demonstrated as accurate methods for extracting detailed topography of integrated circuit structures. However, as critical dimensions become very much less than the current minimum measurement wavelengths and as film thicknesses are simultaneously reduced, there are significant questions regarding the long-term usefulness of this method. In this paper, I will attempt to address some major aspects of this problem.

A very fast and accurate forward scattering method has been developed and implemented for detailed lithographic sytems. This method has been employed in an inverse scattering algorithm developed and implemented for various {\it in-situ } metrology tasks. This forward scattering algorithm utilizes complex realization of the permitivity functions of highly lossy materials, obtained from a newly developed algorithm, part of which is employed in the hybrid inverse system. This hybrid system has been devised to predict wafer properties like feature profiles and layer thicknesses. It combines several components due to the inapplicability of standard inve rse methods such as conjugate gradient and Hessian matrix inversion. It is demonstrated that initial and final spectra match. A comparison between measured and evaluated material properties are in very good agreement as well. Examples of stacks, resist feature and profile roughness are demonstrated. This newly developed and implemented methodology is self-contained and can serve as a versatile metrology tool.

ArF resist lines are tested using scatterometry to study the CD correlation with CDSEM, profile variation caused by baking temperature and pattern environment, as well as the evaluation of optical proximity effect (OPE). Results show reasonable profiles variation predicted by scatterometry spectra from different baking temperatures. Other good matches are the predicted resist line profiles from dark-field and clear-field pattern environment and various line-pitch ratios. They are found to be very similar with the images from the cross-section SEM. On the other hand, the CD linearity and OPE are also found with good matches between scatterometry CD and SEM CD. However, the maximum pitch size tested for OPE is 0.6 μm. More sparse patterns aer believed to have lower sensitivity caused by the weak characteristics spectrum detected. The spectrum sensitivity is another important topic in this paper. The CD and pitch information is contained across the entire spectrum while small profile variations, like t-top and footing, are predicted in the shorter wavelength region. To predict accurate resist profile for small CD, the usage of the shorter wavelength spectrum is inevitable.

Scatterometry is a novel optical metrology based on the analysis of light diffracted from a periodic sample. In the past the technology has been applied successfully to a variety of different grating types found in the manufacture of microelectronic devices. The scope of these applications, however, has been limited to structures that are singly periodic (periodicity = 1) in nature, i.e., gratings that are simple line and space structures with one periodic dimension. Rigorous coupled wave theory (RCWT), the underlying theory behind scatterometry measurements, can be applied to structures with a higher dimension of periodicity (periodicity > 1), although the computation is much more complex. In this paper we will discuss the application of scatterometry to structures with higher dimensions of periodicity, such as arrays of contact holes and DRAM cells. Details of the model, such as computation time and considerations for choosing a proper shape for the diffracting structures, will be presented. Sensitivity of the various parameters, such as the multiple critical dimensions and sidewall angles, will be discussed. Finally, results of measurements on contact hole and typical DRAM storage node patterns will be summarized. When compared to SEM, we will show correlation results that are greater than 0.9 for most applications, indicating that the technology can be applied successfully to such complicated structures. System matching between tools for these applications will also be discussed.

The measurement of critical dimension for materials intended for use in manufacturing devices with features of 150nm or less is a significant challenge. Currently available metrology is inadequate at providing robust measurements with the precision and accuracy needed to quantify differences. The added challenge needing to understand the impact on process and material changes on profiles further complicates the analysis of the these data. The further challenge of measuring contact holes or vias smaller than 200nm for size and shape as well as profile is an essential but elusive need for all CD metrology. CD Scatterometry shows great promise in meeting the precision and accuracy needs of current and future metrology needs. First generation library-based solutions showed great capability, but were limited in their sensitivity and flexibility. We report here the results of using next generation optical metrology equipment coupled with robust real-time analysis software to measure the critical dimensions on several difficult organic films on production and research levels. Demonstrations of capability and flexibility of measurements of various linewidths and pitches across 248nm and 193nm technologies, as well as contact hole metrology, will be featured. Special focus on sensitivity to material and process variability and intentional changes will be included. Specific examples of production level decision guidance based on real-time critical dimension measurements will also be presented.

We have developed fast numerical solutions to the diffraction of light from a periodic array of contact holes (CH) in microelectronic structures. We present results for contact holes in oxide and in 193 nm and 248 nm photoresists. We also show detectability limits of the CH and observed variations across wafers processed with state-of-the-art lithography.

A preponderance of critical levels for the 90-nanometer (nm) process technology node utilize 193 nm lithography. The resist systems used in this processing show a much higher sensitivity to line width slimming at the traditional electron beam energies encountered in Critical Dimension Scanning Electron Microscope (CD SEM) metrology than do previous generations of chemically amplified resists. The uncertainty that results from this undesirable interaction can consume more than the entire process control budget for advanced devices. This paper reports measurements of resist CD uniformity taken with a new CD SEM metrology technology based on ultra low voltage, that significantly reduces the impact of the electron beam on 193 nm resist systems. Over the past several months this technology has been used for 193 nm resist development studies at ARCH Chemicals. Several examples, demonstrating the effectiveness of this new technology using the Yosemite Ultra Low voltage CD SEM will be presented and contrasted against results obtained at higher voltages.

ArF resist slimming under electron beam exposure introduces significant measurement uncertainty in the metrology of 193nm resists. Previous studies have demonstrated the primary effect of electron landing energy on ArF resist line slimming; this work examines the influence of acquisition time, beam blanking, probe current and measurement magnification. This work will demonstrate, in concurrence with other research, that reducing landing energy remains the most effective method for minimizing line slimming of ArF resist under electron beam exposure. However, the other parameters studied can also affect the magnitude of line slimming. This becomes especially important for line edge roughness (LER) measurements which require a greater total dose be imparted to the sample to maintain measurement precision. Control over all acquisition parameters is essential to achieve accurate and repeatable LER measurements.

This study presents a method of extracting 3D metrological information for etched gate structures from top-down SEM images for use in critical dimension analysis. The variations in sidewall angle and bottom corner roundness are quantified as feature indices by multiple parameter profile characterization (MPPC), and are used as the main indicators of device performance. A stable algorithm developed based on simulation and experimental results partitions the SEM image signal into the sidewall and footing based on the first derivative of the image signal. The width of the sidwall is used as an index of the sidewall angle, and the width of the footing is used as an index of the footing roundness. The validity of the MPPC method is confirmed through experiments using actual poly-Si gate wafers, and is shown to have a 3σ accuracy of ±0.9° for sidewall angles deviating by mroe than 2°. The sidewall angle index and its distribution map are useful for evaluating the etching process, and are particularly effective for revealing subtle macro variations like asymmetry, while the footing roundness index is useful for screening out bad wafers. As MPPC employs only top-down SEM images, no throughput loss will be incurred in comparison with conventional CD measurements.

We have developed a new atomic force microscope method that we call Step-in mode. The Step-in mode can realize a high aspect ratio structure observation without tip damage becasue of its unique probing method. Three types of high aspect ratio probe, a silicon probe sharpened by focused ion beam, a high density carbon probe and a carbon nanotube probe, are analyzed to make clear which probe is appropriate for high aspect ratio structure metrology. It is demonstrated that fine measurement can be carried out with all types of probes and we conclude that the high density carbon probe is the best at the present time. Experimental results show that the pitch repeatability for a standard grating sample is 1.2 nm at 3σ, height repeatability is 1.2nm at 3σ and width repeatability of a poly-silicon gate with side-wall is less than 3 nm at 3σ. It is also demonstrated that there is no tip damage after taking 1000 profiles of 512 data points in the Step-in mode. The experimental results show that the Step-in mode. The experimental results show that the Step-in mode has a potential for application to critical dimension metrology for a LSI process monitor.

Measurement precision to process tolerance ratio (P/T) is an essential indicator of metrology readiness for a specific technology. A smaller ratio improves the process control achievable with a given metrology. The International Technology Roadmap for Semiconductors is calling for P/T of 0.2. The 'precision' (P) represents total uncertainty of the measurement. In practice P is estimated as the total variation of measurements made on a reference sample(s) over an extended period of time. This procedure leaves sample-to-sample variation of measurement bias outside of P (measurement bias is the difference between reported average and true value). We report on sample-to-sample CD SEM bias variation as characterized by CD AFM. CD AFM is virtually immune to material, layout and line profile variations and, therefore, is expected to have negligible sample-to-sample bias variation. We found that sample-to-sample CD SEM measurement bias variation (full range up to 15 nm) is often comparable to or even exceeds CD SEM reproducibility (full range of ~ 3 nm). Therefore, the current methodology of the 'precision' measurement is leaving a significant component of the total measurement uncertainty unaccounted. The sample-to-sample bias variation measured on a set of samples representative to the specific technology needs to be corrected or added to the tool reproducibility in order to estimate total uncertainty of measurement. This may noticeably change the 'precision' of CD SEM and move P/T for the current 130 nm and 100 nm technologies well over the limit of 0.2. Should the industry keep CD SEM as a major in-line CD across chip metrology the sample-to-sample bias variation has to be significantly improved. Otherwise, chip manufacturers will likely fail to deliver required across chip gate CD uniformity.

Accuracy in CD-SEM metrology is divided into two discrete categories. The first category is the certification of the measuring tools' (CD-SEMs) magnification behavior. This involves magnification stability, magnificaiton linearity and magnification calibration to a certified reference. The second category is the interpretation of physical feature dimensions from their representation in the CD-SEMs digital image. To date, the algorithms used to interpret physical dimensions from CD-SEM images trace their history to image analyiss algorithms developed decades ago. This paper evaluates the currently used feature analyiss algorithms available in commercial CD-SEMs and compares their behavior to a newer approach developed by nanometrology. Measurement algorithms must be stable and not contain arbitrary free parameters. In addition, the basis for the contruct of the algorithm should be founded on an understanding of e-beam sample interactions and the resulting video signal profiles resulting from this interaction.

Because of their high quality, repeatability, and non-destructive nature, CD-SEMs are the gold standard for metrology in the fab. Yet, there are known offsets from this metrology type compared to others. For example, there is an inherent bias in the measurements made on the top down CD-SEM relative to measurements made from cross-sections. The underlying causes for this bias are complex, and are related both to the measurement techniques used and the interpretation of the data in terms of a specific measurement model. In extracting a line width measurement from a CD-SEM line-scan, for example, the line-scan analysis algorithm interacts with the resist profile shape to produce reported CD. The influence of the resist profile shape on the CD for top down measurements will, in general, be different from the influence of profile shape on a cross-sectional measured CD. We present here a study of CD metrology made with top down CD-SEMs and the corresponding cross-sectional metrology taken from the same structures on the same wafers. The experimental data show the top-down to cross-section offsets to be small, but present over a variety of profile shapes and measurement algorithms. We then use a simple simulation of a typical CD-SEM measurement to predict the offset as a function of beam properties, material composition, and profile shape of the structures being measured. We compare our simulations with the experimental data, tuning the model to give accurate results for our test structures. In this manner, we hope to adequately predict the top-down offset and thereby eliminate it as a source of error in calibrating a lithography simulator.

The measurement of line-edge roughness (LER) has recently become a major topic of concern in the litho-metrology community and the semiconductor industry as a whole, as addressed in the 2001 ITRS roadmap. The Advanced Metrology Advisory Group (AMAG, a council composed of the chief CD-metrologists from the International SEMATECH consortium's Member Companies and from the National Institute of Standards and Technology, NIST) has begun a project to investigate this issue and to direct the CD-SEM supplier community towards a semiconductor industry-backed solution for implementation. The AMAG group has designed and built a 193 nm reticle that includes structures implementing a number of schemes to intentionally cause line edge roughness of various spatial frequencies and amplitudes. The lithography of these structures is in itself of interest to the litho-metrology community and will be discussed here. Measurements on different CD-SEMs of major suppliers will be used to comparatively demonstrate the current state of LER measurement. These measurements are compared to roughness determined off-line by analysis of top-down images from these tools. While no official standard measurement algorithm or definition of LER measurement exists, definitions used in this work are presented and compared in use. Repeatability of the measurements and factors affecting their accuracy will be explored, as well as how CD-SEM parameters can effect the measurements.

A guideline for evaluating LER and total procedure to estimate effects of measured LER on device performance were proposed. Spatial-frequency distributions of LER in various resist materials were investigated and general characteristics of spatial-frequency distribution of LER were obtained. Measurement parameters for accurate LER measurement can be calculated according to the guideline. Measured line-width distribution was used for predicting degradation and variation in MOS transistor performance using the 2D device simulation. Effect of long-period component of LER was clarified as well as short-period component.

The Apparent Beam Width (ABW) total system resolution metric is part of the International SEMATECH CDSEM specification and bench marking activities. It is also used in our own CDSEM specification, evaluations, and tool maintenance activities. Our first set of ABW artifacts, constructed a few years ago, need retirement for several reasons, including: (1) their materials and dimensions no longer represent current manufacturing line samples and (2) their line edge variation is too large for current and future ABW applications. The construction and testing of a new ABW artifact will be discussed in this paper. The use of ABW as a monitor for total system resolution requires a unique set of sample characteristics, which include near vertical sidewalls, minimal top corner rounding, minimal line edge roughness (LER), and good line edge uniformity across the artifact set. Several process iterations were performed using the latest photolithographic processes whilst including numerous measurement evaluations in order to achieve these characteristics. A sampling methodology has been formulated to take advantage of the good within-field, field-to-field, and wafer-to-wafer uniformities of the artifacts. In addition to driving resolution improvements ABW also serves as a metric for tool-to-tool matching in a manufacturing environment.

This paper is a practical guide to the calibration of magnification of a CD-SEM using a pitch standard. It answers two fundamental metrology questions: 1) how many individual pitch measurements should one take in order to estimate the average pitch of the sample with a specified uncertainty and with a specified confidence level?, and 2) when is it appropriate to recalibrate the instrument following the measurement of the standard? In answering these questions, this paper identifies Cost of Ownership (CoO) elements of the calibration process and outlines best engineering practices for the calibration procedure. The discussion is then extended to the case of tool matching and calibration of not just a single measurement tool, but an entire measurement system comprised of several measurement tools all matched to each other. Finally, this paper discusses the problem of hydrocarbon contamination in a CD-SEM, which limits the number of times that a certain location on the standard can be used for calibration, and presents a methodology to determine how often the measurement location should be changed.

The image quality of an inspection microscope depends strongly on the performance of the illumination system. Especially in the case of laser-based illumination it is necessary to transform the original beam profile into a homogeneous light spot with a flat top field distribution. Simultaneously, speckles caused by the coherence of the laser have to be reduced. Here we discuss different ways to homogenize the multi mode beam profile of a pulsed compact 157 nm excimer laser. A variety of setups, combining dynamic acting diffusers, microlens arrays and primary lenses were realized and characterized in several geometrical arrangements. The homogenizers were evaluated and characterized especially with respect to the statistical behavior on the integrated pulse number.

A real-time inspection is useful and effective to optimize lens aberrations of excimer-exposure sytem, which can expose patterns less than 100 nm. We have developed a portable i.e., compact and lightweight phase measuring interferometer (P-PMI), which can be attached to a stage of the exposure system during real-time monitoring the aberration of the projection lens mounted on the exposure system. Measured repeatability of the wavefront measurement is ab out 0.1 mλ and tool-to-tool difference is 0.6mλ. Measured wavefront during adjusting a projection lens agree dwell with a simulated result. LWA was successfully optimized using P-PMI data.

A high-speed image processing has been created. Distributed computing is used to get the necessary resources. Controlling a high-resolution microscope, the image processing system grabs thousands of single images from different XYZ-positions. The system can get all available optical information from a greater microscopical structure like a complete chip on a wafer. Image pre-processing functions are used to eliminate optical effects like shading. A digital contrast enhancement is also available to get a better image quality. The scanning process can take several hours if a high-aperture objective lens is used. At the end we have a complex cluster image structure, and after the image post-processing the creation of the mosaic image can be started. The post-processing functions reduce the 3D data to 2D data. Best focus images can be defined or extended depth of focus images can be created. XY-neighboring images have overlapped areas. In two runs a correlation function define offset values. In a XY-run all available offset values define the final offset values. The result can be checked and manual changes are possible before writing the final mosaic image file.

This paper discusses potential sources of contaminants, their impacts on lithography processes, and the possibility of solving such problems using SMIF technologies. Theoretical models are developed and experimental data are presented.

This paper obtains basic numerical data fro measuring linewidths using light waves to contorl the sub-100nm resist and silicon linewidth. We use the finite-difference time-domain (FDTD) method as the numerical analysis method, becuase the method can consider the losses of permittivity of the resist and the silicon substrate. The linewidths are 2D on the assumption that they are uniformed in the same direction and the 2D Gaussian beams are irradiated. The TM modes with only electric fields and the TE modes with magnetic field polarized parallel to the trench are irradiated. Then, we examine the differences of complex amplitude reflectance by changing the groove widths and thickness of the resist and silicon. Since the TM modes have the cutoff property and the TE modes do not, the amplitude and the phase changes of TM modes are different from the TE modes. Especially, the phases change in linear and in proportion to the groove widths and depths. The amplitude relfectance characteristics of the reflected waves are also examined in changing the incidence angles and the wavelengths of the Gaussian beam. Finally, we confrim teh FDTD analysis is effective to obtain the reflected light characteristics close to the real photolithographic models.

A key enabler to a successful process development and to the device functionality is the introduction of a proper metrology framework, consisting in the selection of the 'correct' tool class for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand. The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update. In order to investigate in deper details the actual status of each selected technique, a list of key characteristics was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy and 'Combo' approaches. Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node proces development are presented.

The increasing of wafer size from 200mm to 300mm and downscaling of IC design rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment and overlay measurement. In this paper, we present a concept of total process control of alignment and overlay, which we had used to get deeper understanding of our metal process with W-CMP and aluminum sputter. Traditionally, a lot of works are focusing on alignment process control and overlay process control separately. However, based on what we had observed, the final overlay performance is largely affected by the difference between alignment system (alignment mark, alignment sensor and process) and overlay system (overlay mark, overlay sensor and process). Deeper understanding of this difference between alignment and overlay system do help us to get better overlay process control o and process/tool matching.

As critical-dimension shrink below 0.18 μm, the SPC (Statistical Process Control) based CD (Critical Dimension) control in lithography process becomes more difficult. Increasing requirements of a shrinking process window have called on the need for more accurate process control. So Advanced Process Control (APC) is going to be a must in the future deep sub-micron lithography, especially 0.18 μm and below. Successful implementation of APC into photolithography depends on how accurate we can determine exposure and defocus from in-line production wafer. Traditionally, in-line process control is based on single structure CD measurement, normally of the smallest dimension as per design. However single import is not enough to predict exposure and focus drift simultaneously. So a lot of studies were done on how to extract exposure and defocus information from in-line CD measurements. And one of these methods is to distinguish focus from energy by monitoring multi-structure CD (CDs of iso/dense, line/pillar and space/hole etc) on normal production wafer. In this paper, we will give a description of this concept. And from that we can see the advantages and drawbacks of this method. Photolithography Simulations (on Prolith) will be carried out to understand the problems we are facing to implement this method into tool matching and inline process control. Finally, we will also propose a new approach to overcome the drawbacks of this method.

The Overlay Metrology Advisory Group (OMAG) is a group comprised of technical experts in the field of optical metrology from International SEMATECH Member Companies and the National Institute of Standards and Technology (NIST). This council created a specification for overlay metrology benchmarking which indicates the critical parameters to be addressed in order to comply with the International Technology Roadmap for Semiconductors (ITRS) for the 130-nm technology node. A benchmarking study was completed that compares several of the currently available overlay metrology tools. This paper contains the methodologies for benchmarking overlay metrology tools, a comparison of repeatability, reproducibility, throughput, tool-induced shift (TIS) variability, accuracy, and TIS through focus measurements between the participating tools. The tools were identified to the International SEMATECH Member Companies and the appropriate tool suppliers. The identity of the tools will remain only with these select groups. This paper intends to serve as a reference to the current tools' ability to meet the ITRS Roadmap specifications for the 130-nm technology node.

The dielectric function spectra of low dielectric constants (low-k) materials have been determined using spectroscopic ellipsometry, normal incidence spectroscopic reflectometry, and Fourier transform infrared transmission spectrometry over a wide spectral range from 0.03 to 5.4 eV (230nm to 40.5um wavelength region). The electric and ionic contributions to the overall static dielectric constants were determined for representative materials used in the semiconductor industry for interlayer dielectrics: (1) FLARE - organic spin-on polymer, (2) HOSP - spin-on hybrid organic-siloxane polymer from the Honeywell Electric Materials Company, and (3) SiLK- organic dielectric resin from the Dow Chemical Company. The main contributions to the static dielectric constant of the low-k materials studied were found to be the electric and ionic absorption.

CDU is probably one of the most important process control parameters for poly gate printing process. As the design rule has been shrunk to below 100nm node and k1 approaching 0.35, the required specifications for CDU are more stringently tightened. For low k1 lithogrpahy, optical proximity effect can severely impact CDU of the cirtical features from different neighboring environments, such as, isolated versus dense regions, or near the crowded corners and intersections, etc. Conventional model OPC has been assumed to correct mask feature CD at a best process setting condition. The approach has been widely adopted but it is increasingly becoming less satisfactory since this method does not take into account the process variation within the acceptable process window. In ASMLs LithoCruiser, for a selected CD cut-line, we use a Monte Carlo approach to randomly generate process conditions within the process window to simulate thousands of CDs. Based on the predicted CD distribution, we can calculate the predicted CDU Yield within the process window. Using LithoCruiser's Application Programming Interface (API) we can set up an optimization loop to adjust mask feature snippets for a desired imaging and process condition to achieve user specified CDU yield. Depending on the neighboring environment, mask snippets with the same target CD may need different biases and so are the features with different target CDs due to different degrees of optical proximity effects.

As critical-dimension (CD) shrink below 0.18um, CD control becomes a major concern. Normally there are four approaches to improve CD control: to improve intra-field, intra-wafer, inter-wafer and inter-lot CD uniformity. In this paper, we propose a simple method to improve intra-wafer CD uniformity by optimize developing recipe. In DUV photolithography, intra-wafer CD variation is the major contributor to the overall CD variations. However there are many factors that may impact intra-wafer CD uniformity: Photoresist thickness uniformity, PEB uniformity, wafer surface roughness, substrate reflectivity and developing uniformity, so the situation become very complicated. In our studies, we tried to focus mainly on the developing uniformity of DUV process. To isolate the impact of developing method from other process factors, we proposed a simple method to check developing rate (Rmin) uniformity by photoresist thickness measurement. With this method, we had save a lot of time and manpower in developing recipe tuning and also had a deeper understanding of developing process of DUV resist.

Resist critical dimensions (CD) and thickness are usually obtained by in-line CD SEM or in-line optical metrology measurements but varification or calibration of these is typically achived by cross sectional SEM. As we push CDs to 100nm and beyound, descrepencies between these two sources data can constitute a large percentage of the target dimension. Particularly for 193nm resists, the CD shrinkage under SEM has been well characterized, but the vertical and horizontal compaction behavior in across sectional SEM has not been explored. In this paper, the discussion is divided into two parts. One is for bulk resist and another is for patterned resist. For bulk case, the the only variable is vertical thickness. The experiments for I-line, 248nm and 193nm resist indicated that the resist thickness from the cross sectional image is strongly dependent on the resist polymer structure, the SEM conditions and the interrogration time under SEM E-beam. Therefore, the thickness comparison between optical and electronic is not always meaningful because the cross sectional thickness often shows a low thickness than the optically determined value. We have determined the optimum SEM condition to minimize vertical compaction. There are two variables for patterned resist, vertical thickness and lateral CD size. Our experiments for I-line and 248nm resists exhibited that the patterned resist thickness can be 30% lower than the optical thickness. However, the lateral CD sizes showed less variation relative to the different SEM conditions. The unique behaviors of 193nm patterned resist are also displayed and discussed in this paper. Based on all experimental data, different SEM conditions are recommended based on different purposes to generate accurate cross sectional resist images.

Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.

Etching is one of the important processes of semiconductor production. In this study, we monitored surface etching process, which is used for dielectric barrier discharge (DBD) at atmospheric pressure and room temperature, of photoresist (PR) on Si wafer by using rotating compensator spectroscopic ellipsometry (RCSE). Ellipsometry has mono-layer sensitivity and we can use it in a severe atmosphere such as a reactive gas, plasma and high temperature etc. Also, it is possible to perform non-destructive, real-time, and in-situ measurement. DBD reactor used 20 kV pulse power. We used alumina as dielectric material. The atmosphere of DBD plasma was operated without dark period in optimal frequency. We used 248 nm PR as sample. The PR is coated by spin coater on Si wafer with 248 nm anti-reflection coating (ARC), and wafer is baked after that. Samples are not exposed and are not developed, but are etched after bake. The PR is removed linearly with respect to time and temperature. We obtained several results at various experimental conditions - temperature, gas flow, process time and frequency. On the assumption that PR is removed homogeneously, we can calculate the etching rate by continuous measurement of thickness of PR by ellipsometry.

Advanced stepper or scanner needs extremely high accuracy alignment system. This alignment accuracy is mainly affected by the errors caused by mark deformations and by optical system. To improve the alignment accuracy of our wafer alignment system called 'FIA' we have developed a method called the 'FFO'. Our studies have already shown that FFO has the effect of reducing the errors caused by mark deformations. To examine the errors caused by optical system, new approaches are adopted. In the new approaches a simulation method and a suitable experimental are used. The simulation results by the new method, Spatial Frequency Analysis of Image, show the relation between defocus and the errors caused by optical system and the superiority of FFO. Suitable experimental system brings us the same results as the simulation method. As a result, FFO also has a positive effect on the errors caused by optical system. FIA with FFO is much more accurate alignment sensor for ULSI production.

Resist patterns for ArF-laser lithography slim by electron radiation in Critical Dimension-Scanning Electron Microscope (CD-SEM). To estimate initial CD that includes no LWS, the CD at 0th measurement was extrapolated from shrink-curve that indicates the slimming. Invisible slimming, occurring between the 0th and 1st measurement, was estimated. We made software for CD-SEM to calculate the 0th-CD. Estimation error in the extrapolated 0th-CD was estimated less than 0.9 nm, and the overall slimming including the invisible shrink was 0.3 nm in line-shaped patterns.

A novel actinic (at-wavelength) inspection tool for detecting critical phase defects in extreme ultraviolet (EUV) multilayer-coated mask blanks is designed and being developed. Block inspection by actinic dark field imaging using a combination of Schwarzschild optics, a CCD, and a laser-produced plasma (LPP) light source is employed to improve detection sensitivity while keeping decent throughput. To optimally configure optics and a mask blank within currently available options, EUV scattering from both Gaussian-shaped multilayer defects and surface roughness is simulated. Intensity of the roughness-induced scattering into the imaging optics is computed assuming 0.15nm root-mean-square (RMS) of the multilayer surface roughness with a typical power spectral density (PSD) function. Possible configuration candidates are compared in detail to detect phase defects with its size down to 30nm. We have modeled noise intensity based on the optimum configuration by integrating shot noise and spatial fluctuation of roughness. Pixel-to-pixel fluctuation of background intensity due to spatial roughness variation is studied using random fractal model to be built into the total noise model. Under the criteria of minimizing nuisance defects and maximizing capture rate of real defects, the required specifications for the power and the brilliance of the light source are computed and discussed.

Overlay mismatch of pre/post etch on metal layer is caused by asymmetric metal deposition on overlay mark. The major components of the mismatch are known to be composed of wafer scale and rotation caused by self-shadowing effect and CMP process, respectively. The behavior of each component was observed according to the changes in overlay mark shapes, metal thickness and CMP process conditions in this study. The overlay difference according to metal overhang on overlay mark was also investigated. It was found that overlay mismatch was reduced when the metal overhang on overlay mark happens, and over-polishing overlay mark during W CMP prevents formation of the metal overhang and increases wafer scale mismatch.

The spectral response of transparent quarter micron lines in opaque Chromium layers has been studied with visible light. These lines are design elements of binary components used in advanced optical systems for microlithography. In the current fabrication process lines of 200nm line width and more than 20 μm length are fabricated by electron beam lithography. The geometric parameters of these lines, e.g. width, length and the microstructural quality are controlled by scanning electron microscopy (SEM). In this work want to report about a new possibility to control the optical properties of quarter micron lines with respect to line width and microstructure. We have performed spectral resolved measurements with a tuneable light source in a spectral range between 450nm and 1600nm. Due to the dimensions of the quarter micron lines polarization depend transmission properties are expected. By performing polarization sensitive optical measurements we are able to distinguish quarter micron lines with different widths below the resolution limit of the classical microscopy with visible light.

In this work the profile reconstruction capability of the Appplied Materials NanoSEM 3D CD-SEM is evaluated. The system allows the fully automatic reconstruction of profiles by evaluating profiles measured at two different beam tilt angles. From two different tilt angles up to 15 degrees the reconstruction of side-wall profiels is possible in a quick and non-destructive way even for negatively sloped profiles. The sensitivity of profile reconstruction especially with respect to height and undercut detection in dependence of structure height and beam tilt angle is discussed. We investigate precision and accuracy of profile reconstruction by comparing results from profile reconstruction to AFM and X-SEM results. We show that the side-wall angle can accurately be detected for 193nm resist structures even for negatively sloped profiles. This enables the system for the production use especially for monitoring of such profiles which cannot be detected by top-down CD-SEM so far.

This paper focuses on the problem of obtaining and characterizing the edge roughness of photoresist lines by analyzing top-down SEM images. AN off-line image analysis algorithm detecting the line edge and an edge roughness characterization scheme, based on scaling analysis, are briefly described. As a result, it is suggested that apart from the rms value of the edge, two more roughness parameters are needed: the roughness exponent α and the correlation length ξ. These characterize the spatial complexity of the edge and determine the dependence of sigma on the length of the measured edge. Completing our previous work on the dependencies of the roughness parameters on various image analysis options, we examine the effect of the type of noise smoothing filter. Then, a comparative study of the roughness parameters of the left and right edges of resist lines is conducted, revealing that the sigma values of the right edges are larger than those of left edges whereas the roughness exponents and the correlation lengths do not show such trend. Finally, the relation between line width roughness and line edge roughness is thoroughly investigated with interesting conclusions.

The rapidly emerging Optoelectronics market is bringing new challenges to the lithographer. The production of very large devices, such as waveguides, has historically utilised contact printers to manufacture many devices with both large field size and relatively large dimensions. However, the devices being manufactured today have dimension requirements well below that possible on either contact or projection aligners. As a result of this, i-line lithography is now seen as almost standard, with some leading edge companies producing devices with dimensions that require DUV lithography. An obvious outcome of this is the need to stitch fields together in order to print these relatively large devices, further complicated where i-line and DUV lithography solutions are used, due to the majority of i-line tools being 5X reduction steppers whereas most DUV tools are 4X reduction scanners. In this paper we show results from stitching of multiple reticle fields on i-line steppers and DUV scannners as well as the interdependence between scanner and stepper fields. Experimental results will show that, through various techniques such as field rotation or field magnification, the stitch accuracy can be adjusted. We will also show that this can be applied not only to the complete length of the stitched field, but also to a specific part that may encompass only the device being stitched. Data will show the ability to stitch successfully 5X to 5X, 4X to 4X, and 5X to 4X. In order to measure the accuracy of the stitched field, an overlay tool using box in box structures is normally used. We will show that an exposure tool can use its self-metrology to measure the accuracy of the stitch. The accuracy and repeatability of these measurements as well as a comparison to a typical overlay tool will be given.

After the introduction of the ATHENA^TM alignment sensor, advanced applications of the sensor data are becoming increasingly important to meet the tightening overlay specifications for future technology nodes. As part of the total overlay budget, the effects of different alignment strategies on overlay performance need to be investigated. Keeping in mind that such strategies are simple and easy to use, two developments are addressed in this paper: advanced alignment recipes and advanced mark designs. An alignment recipe defines which signals from the sensor are used to calculate the aligned position. By making advanced use of the available data, wafer alignment can be made more accurate and more robust to processing effects. It is shown that the new Smooth Color Dynamic alignment recipes exhibit good overlay performance on STI, Cu dual damascene and W-CMP / Al-PVD layers. Since Smooth Color Dynamic also takes away the choice of a particular color in the alignment recipe, it is the preferred alignment recipe for all product layers. The optimum design of an alignment mark depends on the process characteristics. As the process characteristics may vary over time, the optimum mark design can change accordingly. To cover a larger process range, multiple alignment mark designs are combined in a new multi-grating mark: the Versatile Scribeline Primary Mark (VSPM). By measuring all gratings during regular production, the optimum grating of a VSPM can be selected and aligned with a Smooth Color Dynamic alignment recipe. For CMP layers a further overlay improvement can be achieved if all gratings have comparable phase depths. By combining alignment signals from different gratings in a predictive alignment recipe, wafer-to-wafer variations due to CMP effects can be reduced.

The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. The mask error enhancement factor (MEEF) describes the phenomenon in which errors in the mask critical dimensions (CDs) are not transferred to the wafer in direct proportion to the optical reduction value of the lithography system. In the low-k1 area, the MEEF becomes a significant problem, as it consumes a larger than anticipated percentage of the CD tolerance budget. As a result mask CD uniformity requirements have been tightened significantly to find MEEF-related CD defects prior to the first printing at the wafer fab. The challenge for today's mask inspection methodology lays in the way defects are detected. Conventional mask inspection detects defects according to their dimensions on the mask. Finding MEEF-related CD defects is a challenge as these defects are often caused by CD deviations close to metrology resolution. The paper investigates CD uniformity control using aerial image based mask inspection. The fundamental difference to today's inspection methodology is that a defect is detected based on its impact onto the aerial image projected by the given mask. In order to emulate the aerial image, lithography condition like Numerical Aperture and illumination need to be known to the inspection system. As a large portion of the MEEF is based on the lithography exposure system, MEEF defects can be detected.

The characteristics of the carbon nanotube AFM tip was investigated as it is used to measure the critical dimensions in the high aspect ratio structures. The research has been done to demonstrate the limitations of the CNT probe in imaging steep or vertical sidewall. Two kinds of samples, silicon dot and the lines in the ArF resist pattern were profiled by using carbon nanotube tip in the tapping mode AFM. There is a large oscillation at the steep sidewall, which cannot be controlled by merely changing scan variables, except by slowing down the scan up to the impractical level. The interaction between the long, slim CNT probe and the vertical sidewall severely limits the usefulness of AFM as a CD metrology tool. To achieve hi-resolution and high aspect ratio imaging simultaneously, a stiffer and/or modifed probe under clever non-contact 2D feedback is needed.

Electron-beam-stimulated etching has been investigated as a clean, alternative method for nanoscale selective processing. Primarily fluorine-based precursors have been used to etch a variety of technologically relevant materials. Empirical data reveals that with decreasing the electron beam energy increases the material removal rate, however the effective beam width increases. Both of these observations are consistent with the fact that cross-sections for electron-gas scattering increases with decresaing beam energy. Monte Carlo models of the electron-gas and electron-solid interactions have been performed to better udnerstand the fundamentals of the process. Finally, specific application to soft transmission electron microscopy sample preparation is made.

We have developed a new system, 'PF-3000', which realizes the pattern shape comparison between CAD layout data and CD-SEM images. Comparison results are expressed as the difference of edge location and area in this system. Moreover, we investigated different methods of shape comparison. Fourier descriptor is one of the most useful method.

A novel approach for determining the drift behavior of an SEM with high precision in 2D space is presented. David Joy described an indirect proceudre for qualitatively detecting image drift in the time domain using FFTs of sequential images. SEM metrology is based on first acquiring an image representation of an object. In this paper, we present a direct approach for quantifying SEM image drift. The next step is applying various algorithms which attempt to determine feature boundaries. The above sequence is based on a stable SEM performance during teh image acquisition interval. If movement of the feature within the imaged field occurs during the acquisition interval, a distorted stability is a critical precursor for precision SEM metrology. We will describe a novel approach for quantifying SEM drift with a precision greeater than 0.2nm within an image field.

The paper examines the viability of various levelling options1 on Nikon i11, i12 and i14 steppers in compensating for across field differences in focus position. The analysis was performed on both production wafers at various processing stages and test wafers with oxide deposited then etched to different depths. The main analysis technique used was the stepper focus measurement system along with Hitachi 9220 CDSEM measurements and levelling beam analysis using a CCD camera2. The conclusion from the paper is that due to diffraction effects of the levelling beam, levelling-on can introduce large wafer stage tilts and so reduce CD control in the i11's and i12's. Since the EGL method also uses the levelling sensor in conjunction with the focus sensors this also introduces large tilts causing large across field CD variation.

The continual improvement of productivity is an area of increasing importance in all aspects of semiconductor manufacturing. It is of especially high priority in the Photolithography sector where equipment costs are the greatest. The overall success of the fabricator facility hinges on the productivity level of the manufacturing equipment. The majority of photolithography exposure systems in use today are configured in a linked mode of operation with a resist coater/resist developer track. This configuration, called a cluster, makes their productivity level directly dependent on each other. One aspect of productivity that has very high visibility is the actual maximum speed of the equipment itself. This paper will demonstrate the ability to improve the productivity of the cluster with Speed Enhancements; however, it will also demonstrate the opportunity for increased productivity through Availability Improvements, and Assist Reduction. This paper describes a very successful application of the analysis of the Exposure system’s equipment logs to: evaluate the Photolithography cluster’s productivity, identify improvement opportunities for the cluster, and serve as a gauge for tracking the gain from implemented improvements. To date, the project described in this paper has identified a path to increase the cluster’s output by more than one hundred wafers per cluster per day.

A methodology is proposed to evaluate measurement correlation and matching feasibility between CDSEMs from different vendors in a multiple tool environment. Two CDSEMs from different vendors are used in this study. The measurement correlation and matching feasibility is identified through a series of steps. The pixel oversampling of both CDSEMs were first adjusted to the same extent in order to achieve the same scan pixel signal-to-noise ratio on both CDSEMs. Then the corresponding linescan smoothing and averaging were lowered but optimized with the precision criterion of less than 2 nm. The scan pixel magnification calibrations on both CDSEMs were traced back to an internal pitch standard. The corresponding measurement linearity was checked against a resolution mask from which wafers with pitch ranging from 400 to 800 nm were generated using a 248 nm stepper. The resulting scanning magnification correction factors for both CDSEMs in two scan orientations were determined for the follow-on measurement corrections on 248 nm resist focus exposure pattern (FEM) wafers and e-beam resist wafers obtained from e-beam lithography. The algorithms' characteristics between two CDSEMs were identified and they were adjusted to use only the information derived from the first linescan derivative in order to maintain maximum algorithm similiarity. The 120 nm process window on 248 nm resist wafers has a positive 1.6 nm offset from CDSEM A to B through focus. Both CDSEMs report the same process latitude for 110 nm process window identification. The measurement correlation study on e-beam resist shows offsets of negative 1.5 and 2 nm from CDSEM A to B, depending on which CDSEM is used first for the measurement sequence. Analysis-of-variance was used to analyze the measurement correlation. It is found that there is no significant difference in offsets generated regardless of which CDSEM is used first for performing the measurement for the 248 nm resist system. However, the offset generated for e-beam resist is dependent on measurement sequence. We conclude that CDSEMs from different vendors can be adjusted to maintain a constant offset over a CD variation range since after tuning all the factors mentioned both CDSEMs have very similar responses toward resist line secondary characteristics. Therefore these two CDSEMs are viewed as matched from a process development and process control prospective. All other CDSEMs in the same vendor group are then matched to each of the two bridged CDSEMs following the correposponding vendor's routine without any major procedure change.

Driven by overlay shrinks and increasing product diversification in advanced fabs, automatic control of correctable overlay coefficients has become critical to semiconductor manufacturing. Although numerous reports have shown the compelling benefits of automatic run-to-run feedback control, one important issue has received very little attention to date. In many state-of-the-art fabs, reticle to wafer alignment is performed against marks that were printed at the first-or zero-level, whereas overlay is still measured between a target level and one or two reference levels. In many cases, perturbations of the reference level are unknown at the time of target level exposure. In this study, we will show how the perturbations of the reference level can impact overlay controllability at cascading levels (levels where overlay is measured against the reference level, but exposure tool alignment is done to the zero level). We will also show that once the perturbation is understood, it can be accounted for at the time of exposure, thus presenting an opportunity for additional overlay improvement.

A polymer etch rate monitor (PERM) was designed to quantify rates of base-soluble polymeric materials by measuring electric signals. The thickness of a thin film was demonstrated to be proportional to the electric resistance of the polymer coating. The applicability of the electric cell design for characterizing the dissolution of polymer coatings was demonstrated. Characterization of the electric signal versus the developing process revealed distinctive steps and mechanisms of the dissolution process. Scanning electron microscopy provided some insight into the dissolution process and the interaction between polymeric coatings and base. The correlation between dissolution rate and the concentration of base was investigated. Also investigated was the relationship between dissolution rate of polymeric coating and its thermal curing parameter. This monitor is able to provide instant information about the dissolution process as well as the etch rate in the base solution. Not only can the overall dissolution rate be measured, but the dissolution behavior and interaction can also be interpreted by analyzing the dissolving curve. This instrument has been used successfully for quality control purposes. Currently, the applicability of this device for photosensitive polymeric coatings is being evaluated.

The latest generations of CMOS are being patterned at decreasing k1 values, which is one of the reasons that their process windows are decreasing. Hence, control of the process gets more and more important and in-die critical dimension (CD) measurements are gradually being introduced for the monitoring of the in-line lithographic process performance. Because an increasingly large portion of the CD-error-budget is already being consumed by the mask-making, there is also a strong tendency toward improving process control of the mask, which in turn leads to a rapid increase in the number of mask-CD measurements even within the die. The main two reasons for the larger contribution of the mask to the error budget at wafer level are: 1) the mask process itself, and 2) the mask-error enhancement factor (MEEF), the magnification factor of reticle-to-wafer error. The latter factor and its lithographic process dependence are very much depending on the shape of a feature and its local vicinity. For example a narrow dense binary line has a larger MEEF than an isolated line and its partial derivative to defocus is much larger. Hence it would make sense to relate such MEEF process-behaviour to the 2D layout shapes in the design and use that as a metric during mask qualification. In this work the Silicon-versus-layout verification (SiVL) tool- inherently an OPC evaluation tool- is used to find such features in the layout that will be most critical for the wafer lithographic process by automatic extraction and selection of their MEEF values. This information can then be used to generate realistic mask specifications and forms a cost-method to control both mask quality and price.

Dissolution rate monitors (DRMs) and related techniques have been used for a number of years to study the dissolution behavior of photoresist materials in detail. Due to the relative difficulty in obtaining commercial DRM instruments, crude methods for measuring dissolution rates such as the (formula availble in paper) have been developed. In this method, the resist-coated substrate is immersed in a developer solution for a fixed development time, removed and dried, and the remaining film thickness is measured. The dissolution rate information for the resist is then calculated from the slope of the resist thickness versus development time data. This method is simple and can easily be used in a fab environment, but it suffers from a number of limitations. For example, this method is very inaccurate for resists that develop very quickly (< 20 seconds) such as many modern chemically amplified resists. Such quick development times are often crucial in exploring the full behavior of a resist. A much better method for measuring the dissolution behavior of photoresist films is to use interferometric methods such as those suggested originally by Dill and coworkers. In this work, an extremely flexible and simple instrument based on inexpensive, commercially available, PC card spectrometers will be presented that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoresist films. The hardware required in order to construct such a simple apparatus will be discussed along with various experimental configurations that are appropriate for different measurement tasks. Thin film thickness estimation using the DRM can be done using either single wavelength versus time interferometry data (plot of reflected light intensity versus development time) or the complete multiwavelength spectra obtained from a spectroscopic reflectometry system. Film thickness estimation using single wavelength data analysis is good for films that: develop completely to the substrate, do not swell during the development process, and do not develop very fast (i.e., > 100 nm/s). Hence for films that either have very long development times (typically very thick films of the order of ~ 5μm), films that have very short development times (usually with dissolution rates exceeding 100 nm/s), or films that swell during development, film thickness determination using the multiwavelength reflectance spectra is the best solution. With this motivation, a multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single and multiwavelength DRM data analysis. It has been found to be very useful in analyzing thin film dissolution data with dissolution rates exceeding 400 nm/s. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. For example, such resist swelling appears to be an issue in the case of resists or other polymers developed or cleaned using high pressure CO2. The basic approaches and algorithms used for thin film thickness/rate determination in MIDAS will be discussed. The advantages and disadvantages of this method will be compared with quartz crystal microbalance techniques as well. It will also be shown that these two methods can be coupled for demanding applications. Results from the use of the MIDAS software in various applications will be presented.

In this work, an extremely flexible and simple dissolution rate monitor (DRM) based on inexpensive, commercially available, PC card spectrometers has been built that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoreist films. The hardware required in order to construct such a simple apparatus has been discussed along with various experimental configurations that are appropriate for different measurement tasks. A multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single wavelength and multiwavelength DRM data analysis. The multiwavelength DRM and MIDAS software have been found to be very useful in analyzing a variety of resist film dissolution phenomena including monitoring films possessing dissolution rates exceeding 100 nm/s and studying resist film surface inhibition/acceleration. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. The basic approaches and algorithms used for thin film thickness and dissolution rate determination in the MIDAS software are discussed in this paper. Results from the use of the MIDAS software in various applications are presented.

The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH consortium's Member Companies and from the National Institute of Standards (NIST). The AMAG wrote, in 2002, with CD-SEM supplier involvement, updated the 'Unified Advanced CD-SEM Specification for Sub-130nm Technology (version 2002)' to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2001 International Technology Roadmap for Semiconductors, and also conveys other member companies' collective needs to vendors. Using this specification, a benchmarking effort of the currently available advanced CD-SEMs will be performed. As these results are not yet complete, they will be presented at a future date. However, the current version of the specification has undergone many changes and improvements from the last, and these will be discussed here.

Scatterometry provides a new, vibration-tolerant technique of overlay metrology. Gauge repeatability and reproducibility is improved by an order of magnitude over imaging-based overlay metrology. To measure the overlay of patterned layers A and B by scatterometry, one line grating is placed in layer A and another in layer B. The two gratings overlap when they are viewed in the direction that is normal to the wafer. The line gratings in layers a and b are of equal pitch and their lines are parallel. In one method, overlay is measured by fitting the optical properties of the target with spectra calculated using a model of the target and rigorous coupled wave analysis. A faster and simpler method obtains overlay by applying a linear estimator to a difference of spectra. Optical properties of targets were measured by a normal incidence spectroscopic reflectometer. Test wafers representing three overlay applications were fabricated: contact mask to shallow-trench, first metal mask to contact, and gate-mask to shallow-trench. Overlay measured by scatterometry agree with imaging-based measurements and offsets intentionally written to the reticle.

Studies on photomask Cr and MoSi etch processes were carried out and etch kinetics and modeling were performed. The photomasks were etched using an AMAT Centura II DPS and compared with a Unaxis VLE 770 ICP etcher. Mask metrology to support theoretical suppositions was performed on several tools: a KLA-Tencor P-12 profiler was used for depth measurement, while the KLA-Tencor 8250XP-R SEM was used for CD metrology and process characterization. The Toshiba EBM3500 50KeV writing system on positive chemically amplified resist was used for pattern creation. Cr and MoSi loading - etch rate equations were theoretically proposed and experimentally tested. It was found that the calculated Cr and MoSi etch rates agreed well with the experimental results. The equations can be used for etch time calculations and endpoint determinations of extremely low Cr load photomasks. Cr and MoSi local etch rates versus local loading on one photomask were studied and kinetic equations were proposed, showing good agreement with experimental results. Cr and MoSi etch CD movements versus local load on one photomask were also investigated. It was found that load effects on Cr and MoSi etch CD movements could be controlled in opposite directions and then a compensation consideration was proposed in MoSi optimization instead of using a point-to-point 3σ as the optimization parameter. By using this compensation method, the final MoSi CD unformity of 100-110 nm technology node photomasks is in the range of 8.5 to 10.1 nm. This final CD uniformity is similar to those etched using VLR 770 ICP etcher.

As design rules shrink and process windows become smaller, strict process control is becoming increasingly important. The two primary process parameters in the photolithography process, exposure dose and focus, require strict control in order to maintain the photoresist profile. This paper presents the second stage of an approach towards monitoring the semiconductor photolithogprhay process by using critical dimension-scanning electron microscopy. In the former paper, we propsed a method that quantifies the photoresist pattern profile variation caused by dose or focus variation. In this paper, a new method for estimating the variation in exposure dose and focus is presented. Top-down SEM imagse are intrinsically limited in the inability to observe the re-entrant profile. This limitation has been overcome through the use of two tyeps of common patterns: island patterns and window patterns. Island patterns, such as isolated line patterns, have a tapered profile for negative defocus, while window patterns, such as isolated spaces patterns, have an inverse tapered profile for negative defocus. Using both types of patterns allows the focus deviation to be monitored, whether positive or negative defocus. The behavior of the two types of patterns is considered here based on photolithography simulation, and a new algorithm for estimating the exposure dose and focsu variation is proposed.

Optical scatterometry and Optical Digital Profiling (ODP) have become mainstram technology in CD and profile metrology. Without question, the extension of these techniques to measure 3D patterns such as contact holes or posts is an important demand. In this paper, we demonstrate the application of ODP to contact holes and posts for both lithography and etch processes. The underlying theory based onthe Rigorous Coupled Wave Approach is outlined and metrology results are compared with simulations.

There is an increasing necessity for 3D measurement of formed patterns in the semiconductor manufacturing process, and the development of the 3D measurement technology is required even in CD-SEM. In order to obtain 3D images, it is necessary to acquire at least two tilted images from different directions. However, the procedure of tilting the specimen stage is disadvantageous from the throughput point of view. Therefore, we devised the T-MOL system, which enables the acquisition of tilt images without the deterioration of the resolution by tilting the primary electron beam. Moreover, the algorithm of the parallel projection for the 3D reconstruction was developed. Tests proved that new T-MOL electron optical system provides 4nm resolution tilting angle at 5 degrees and that 3D analysis based on T-MOL images is effective.

Controlling critical dimension (CD) uniformity and overlay accuracy are crucial to achieving quality lithography. The continuous reduction in minimum feature and unit cell sizes on semiconductor wafers has posed significant strain to lithography engineers. According to the 2001 ITRS roadmap, the half pitch of DRAM will be 100 nm and the overlay requirement will be 35 nm for the Poly layer in 2003. Up to date, the 193 nm lithography is mainly applied to those critical layers, such as Poly, Contact, Metal and Via in chip process flow. For the non-criticals, such as well and source-drain implant layers, we still use 248 nm or even 365 nm lithography. Such a situation poses potential challenges when we try to improve the overlay accuracy demanded by area reduction on unit cells since a mix-and-match between 193 nm and 248 nm has to be carried out. In the 90 nm logic process, the overlay requirement of implant layer to critical layers are tightened to 60 nm, which has been close to the current limit of tool matching capability between 193 nm and 248 nm. Stimulated by such an issue we start to implement 193 nm lithography into implant layers. In this paper, a full lithographic process characterization for 90 nm logic implant layers using 193 nm lithography is reported. The photo resist swing cure was first generated to determine the resist thickness. A top antireflective coating (ARC) was also applied to reduce the photo resist swing effect. After the target thickness of photo resist is being defined, three different thickness of resist was coated including targeted, thinner and thicker than targeted. Resist coated wafers were through bombardment of implantation species, then were sent to SIMS analysis. Based on the SIMS results, the target thickness is verified to be safe for the high voltage implantation required by process flow. The DOF data were collected for six kinds of patterns. The proximity effect data of 193 nm is only half of that resulted in 248 nm lithography. So, the optical proximity correction (OPC) may not be needed if 193 nm lithography is used. Besides, the CD variation is also improved when compared to the 248 nm lithography, especially when resist patterns are printed on topographic wafers. As the chip continues its shrinkage, the 193 nm lithography will be a must for implant layers at some point.

Most chip makers want KrF lithography is extended below sub 100nm lithography due to cost and process stability, even though ArF lithography has been growing and its performance is enough to apply to 100nm node. But process control of KrF lithography will become difficult at sub 100nm node era because of difficulty of mask making, accuracy of optical proximity correction (OPC), lens effects caused by strong off-axis illumination, need more tool accuracies than ever, and so on.

Modern photolithography uses wafer steppers to project the image of a given circuit layer from a reticle onto a photoresist-covered wafer. In the sub-wavelength exposure regime (where the imaging wavelength is greater than the feature being imaged) the wafer surface needs to be positioned within a few hundred nanometers of the stepper focal plane to maintain imaging fidelity. Since typical wafer surface flatness variation is far in excess of this, imaging is accomplished by continuously focussing on the wafer surface during the exposure operation. For 'edge shots', where the centre of the stepper field gets close to the wafer edge, the focussing challenge gets very severe due to increasing wafer flatness variation. The focussing position is determined from the top surface of the resist. However at the edge of the wafer the resist thickness is not uniform, due to effects of the wafer edge bead. This leads to errors in the correct focus offset value been picked to place the wafer surface position within a few hundred nanometers of the stepper focus plane. These variations have a direct impact on yield, especially in sub- wavelength processes, and effects a sizeable proportion of the wafer surface area. This paper describes the yield improvement activities under taken on an i-line 0.35um BiCMOS process. This work comprises of three main parts. The first area investigated, was the changing resist thickness profile at the edge of the wafer.

In order to design a reference suitable for performing CD-SEM magnification calibration with high precision and accuracy it is necessary to first identify the relevant critical issues. We will discuss why the magnification calibration reference is a key challenge; why CD-SEM magnification calibration is not trivial; and why a suitable magnification calibration reference does not currently exist. We will identify the criticalities for the above issues. We will present a novel solution leading to design criteria for a universal CD-SEM magnification calibration reference.

Tight control of very small transistor gate CDs is one of the most difficult problems in advanced device patterning. Line-edge roughness on these small gate lines has become a serious issue with 193nm lithography and is only expected to worsen with 157nm and EUV lithography. Methods are needed that can minimize line-edge roughness while also enabling the patterning of small gate features. We have analyzed the use of a simple and manufacturable post-develop bake step, a 'hardbake', that controllably reduces both gate resist CDs and to line-edge roughness. Hardbake resist shrinkage is a well-known phenomena from earlier Novolak resist processing, but has not been investigated for chemically amplified resists as much as other CD slimming techniques. Our tests have been performed for different chemically amplified 193nm and EUV-type (essentially reformulated 248nm) resists. The results of our experiments show considerable potential for certain types of resists to provide gate CD control benefits from either roughness reduction or CD slimming.

This paper presents the concept of 'copy result exactly' frameworks using EB-SCOPE technology which must be a powerful tool for coping the best process condition producing ever lasting good contact and via hole.

Many advanced wafer fabs are currently fabricating devices with 130nm or smaller design rules. To meet the challenges at these sub-wavelength technology nodes, fabs are using a variety of resolution enhancement techniques (RETs) in lithography and exploring new methods of processing, inspecting and requalifying photomasks. The acceleration of the lithography roadmap imposes more stringent requirements on mask qualification and requalification to ensure that device yields are not compromised: mask inspection tools of today need to find smaller defects on reticles against considerably more complicated patterns or tighter critical dimensions (CDs). In this paper we describe the early stages of implementation and proliferation of advanced reticle inspection tools at high volume manufacturing wafer fabs. The fabs run incoming multi-surface contamination inspections on masks sent from the mask shop (Intel Mask Operations, IMO), and follow them up with periodic inspections/review to make sure any new contaminant or damage does not go undetected. When necessary, images of defects are electronically presented to engineers at IMO for review. Reticle requalification with these inspection tools reduces or eliminates the need for print test verification. We describe the tools and procedure used to streamline reticle requalification at the fabs and improve the feedback loop between the fabs and the mask shop.

As feature sizes shrink, metrology tools are challenged to deliver higher precision. To meet the demands of the semiconductor industry it is critical to determine and eliminate erros induced by metrology tools. It is also critical to investigate error-inducing factors neglected in the past. Image rotation is regularly experienced on a CD SEM, however error induced by it is assumed to be negligible and neglected. Experience shows an inline SEM often has image rotation of as much as ±26.3% of the edge thickness. For the range of rotation often experienced, experimental data fits the theoretical model suggested. Current tool monitoring techniques rely on pitch accuracy to monitor the day to day performance of the tool. Pitch is also used for tool calibration. However, pitch measurements are not significantly affected by image rotation hence using pitch as a standard for CD SEM monitoring is inadequate when dealing wiht a rotated image.

Spectroscopic Scatterometry was employed for definition of control metrics for lithography process tool optimization. Normal incidence unpolarized reflectance data was acquired in active device regions on resist gratings that defined the first gate level for the core array of a flash memory circuit. Calculations of the interactions of incident boradband light with the scattering structures were perforemd utilizing both a database of pre-computed spectra as well as a real-time method. Results from both inversion techniques were highly correlated. Scatterometry-based CDs were also highly correlated with dimensions determiend by CD-SEM and the modeled profiles clsoely matched cross section SEM data. Test wafer sets were patterned both at uniform exposure and as focus-exposure matrices, and measured to determine resist critical dimensions and thicknesses. Process variations were tracked across fields, across wafers and over time. Analytical models were applied to the profile data to determine rpocess windows and to define optimal scanner settings.

A system for monitoring the transient and steady state temperature profiles during the deep UV (DUV) post exposure bake (PEB) is described. The system, called Accura°C, consists of a sensor wafer, a wireless electronics unit and software on a laptop computer. To monitor temperature platinum resistance temperature detectors (RTDs) are embedded into silicon wafers. A flexible high temperature printed circuit (PC) ribbon cable connects the wireless electronics unit to the wafer. The system robot moves both the sensor wafer and electronics unit through the system. Communication between the electronics unit and a laptop computer is accomplished by a Bluetooth RF link. The RF link enables the laptop computer to analyze the temperature measurements in real time. The rechargeable batteries in the electronics unit allow detailed examination of all process chambers. Further the long operating time and real time data stream provide for bake chamber optimization such as tuning. The sensor integration into the wafer provides accurate, artifact free measurements of the rapid temperature changes during PEB ramps.

As fabs transition from 200 to 300mm wafers with shrinking design rules, the risk and cost associated with overlay excursions become more severe. This significantly impacts the overall litho-cell efficiency. Effective detection, identification, and reduction of overlay excursions are essential for realizing the productivity and cost benefits of the technology shifts. We have developed a comprehensive overlay excursion management method that encompasses baseline variation analysis, statistical separation and characterization of excursion signatures and their frequencies, as well as selection of sampling plans and control methods that minimize material at risk due to excursion. A novel baseline variance estimation method is developed that takes into account the spatial signature and temporal behavior of the litho-cell overlay correction mechanisms. Spatial and temporal excursion signatures are identified and incorporated in a cost model that estimates the material at risk in an excursion cycle. The material at risk associated with various sampling plans, control charts, and cycle times is assessed considering various lot disposition and routing decisions. These results are then used in determining an optimal sampling and control strategy for effective excursion management. In this paper, we describe and demonstrate the effectiveness of the methods using actual 300mm fab overlay data from several critical layers. With a thorough assessment of the actual baseline and excursion distributions, we quantify the amount of wafer-to-wafer and within-wafer sampling necessary for detecting excursions with minimal material at risk. We also evaluate the impact of shorter cycle time and faster response to excursion, which is made possible through automation and alternative metrology configurations.

The growing evolution of MEMS devices over the past decade from laboratory R&D environments into volume production settings for consumer use, has required Dimensional Metrology to become an invaluable part of the device fabrication process. In this paper we examine the dimensional metrology requirements for the Inkjet MEMS, and present high precision data obtained at a variety of fabrication stages. The measurement data has been used to guide process control on these structures and ultimately has led to improved device performance.

Current realities of tighter process tolerances combined with continued reduction in engineering resources per metrology tool require that every step of controlling a process a be made more efficient. Analyzing the quality of metrolgoy results, from equipment such as CD SEMs, can involve many factors that include image quality, measurement outputs, focus setting, and amplitude of system settings that play a role in the metrology results. The most efficient means of accessing large volumes of data today is via the World Wide Web. This paper provides examples of metrology problem resolutions that were achieved through the use of WWW on-line analysis of CD SEM results. The relational database that contains the measurement results, CD SEM settings, and metrology and pattern recognition images can be accessed from any fab PC, and can also be accessed from any fab PC, and can also be accessed from outside the fab by personnel with proper levels of security. Simple navigation through a web browser and the completeness of the data in the results database greatly improve the efficiency of the metrologist and the quality of the diagnosis, for improved process control and personal productivity.

As the critical dimension (CD) in integrated circuit (IC) device reduces, the total overlay budget needs to be more stringent. Typically, the allowable overlay error is 1/3 of the CD in the IC device. In this case, robustness of alignment mark is critical, as accurate signal is required by the scanner’s alignment system to precisely align a layer of pattern to the previous layer. Alignment issue is more severe in back-end process partly due to the influenced of Chemical Mechanical Polishing (CMP), which contribute to the asymmetric or total destroy of the alignment marks. In this paper, the performance of different design of alignment marks on 0.10μm echnology wafer has been evaluated using ASML ATHENATM alignment system. For example, segmented marks with smaller dimensions in terms of width and length are used. Narrow marks are preferable due to the space constraint in the scribe lines. The width of NSPM has been shrunk down to 70% of the SPM and the length remains the same. It is a challenge to the alignment system to collect the NSPM signal and provide comparable alignment capability. The evaluations were completed using short loop wafers, which focus on back-end-of-line via and metal layers in a 90nm Cu dual damascene low k process. The results also look into the overlay performance using different alignment strategies. Offline overlay measurements were performed to verify the results.

Airborne contaminants have been shown to cause image degradation to acid-catalyzed chemcially amplified resists at low concentrations. In addition to mitigation measures, choices can be made to remove resist strippers from the DUV fab and eliminate those known to poison the resist. Such choices can be made based on the evaporative alkalinity of the stripper. A method has been developed as a rapid technique for testing the ariborne alkalinity strength of various resist strippers. This screening technique provides rapid information at minimal cost to qualify safe chemical strippers for the DUV fab. Experimental results on resist strippers to include commoditites such as isopropanol, a cyclic ketone, amide, and specialty blends that contain amines as well as a high performance product, GenSolve.

Contacts and VIAs are features whose integrity are very susceptible to reticle CD defects or in general, to defects that produce a change of total energy (flux) projected through the reticle. As lithography is extended beyond the 130nm node, the problem becomes more critical. Detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying reticles to enable high IC wafer yield for the 90nm node. The current state of the art inspection methods are unable to meet the industry requirements for contact and via features. Using the TeraStarTM pattern inspection system's image computer platform, a new algorithm, TeraFluxTM, has been implemented and tested for the inspection of small 'closed' features. The algorithm compares the transmitted energy flux difference between a test contact (or a group of contacts) and a reference image for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Sensitivity characterization tests show that the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts. We performed experiments to correlate the sensitivity performance of the new algorithm with wafer printability results. The results will be presented together with results of inspections results of programmed defect plates and production reticles.

Alignment error that originates in the actual wafer process is one of the factors to deteriorate total overlay accuracy. This error has been called wafer induced shift (WIS). WIS occurs through a change of alignment marks topography under the actual wafer processing. To quantify mark asymmetry WIS, we study the mark asymmetry on tungsten chemical mechanical polishing (CMP) wafers by using an atomic force microscope and define new criterion in this paper. The mark topography of CMP process wafers are measured by AFM and quantified using the new criterion. The asymmetry of the mark topography can be quantified by measuring the profiles of an alignment mark across the wafers. It has been proven, that the rotation error is caused by the asymmetry of the mark topography and the asymmetry is not related to the line width of the mark.

The development of 100-nm design rule technologies is currently taking place in many R&D facilities across the world. For some critical alyers, the transition to 193-nm resist technology has been required to meet this leading edge design rule. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193-nm resits process did not meet the photolithography requirements of some IC manufacturers due to very high Post Exposure Bake temperature sensitivity and consequently high wafer to wafer CD variation. The photoresist vendors have been working to improve the performance of the 193-nm resists to meet their customer's requirements. Characterization of these new resists needs to be carried out prior to implementation in the R&D line. Initial results on the second-generation resists evaluated at Cypress Semicondcutor showed better CD control compared to the aelrier resist with comparable Depth of Focus (DOF), Exposure Latitute, Etch Resistance, etc. In addition to the standard lithography parameters, resist characterization needs to include defect density studies. It was found that the new resists process with the best CD control, resulted in the introduction of orders of magnitude higher yield limiting defects at Gate, Contact adn Local Interconnect. The defect data were shared with the resists vendor and within days of the discovery the resist vendor was able to pinpoint the source of the problem. The fix was confirmed and the new resists were successfully released to production. By including defect monitoring into the resist qualification process, Cypress Semiconductor was able to 1) drive correction actions earlier resulting in faster ramp and 2) eliminate potential yield loss. We will discuss in this paper how to apply the Micro Photo Cell Monitoring methodology for defect monitoring in the photolithogprhay module and the qualification of 193nm resist processes.