2 June 2003 Challenges of image placement and overlay at the 90-nm and 65-nm nodes
Author Affiliations +
Abstract
The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. INTERNATIONAL SE-MATECH has been leading and supporting efforts to investigate the impact of the tech-nology introduction. This paper examines the issue of manufacturing tolerances available for image placement on adjacent critical levels (overlay) at the 90nm and 65nm technol-ogy nodes. The allowable values from the 2001 release of the ITRS Roadmap are 32nm for the 90nm node, and 23nm for the 65nm node. Even the 130nm node has overlay requirements of only 46nm. Employing tolerances that can be predicted, the impact of existing production/processing tolerance accumulation can provide an indication of the challenges facing the manufacturer in the production of 90nm and 65nm Node devices.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Walter J. Trybula "Challenges of image placement and overlay at the 90-nm and 65-nm nodes", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.485036; https://doi.org/10.1117/12.485036
PROCEEDINGS
7 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

Changing technology requirements of mask metrology
Proceedings of SPIE (September 30 2013)
Multilayer overlay metrology
Proceedings of SPIE (March 23 2006)
New directions in image placement metrology
Proceedings of SPIE (April 01 2011)
Image Matching: A Method For Overlay Error Reduction
Proceedings of SPIE (November 06 1983)

Back to Top