2 June 2003 Total process control of alignment and overlay for metal layer
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Proceedings Volume 5038, Metrology, Inspection, and Process Control for Microlithography XVII; (2003); doi: 10.1117/12.482651
Event: Microlithography 2003, 2003, Santa Clara, California, United States
Abstract
The increasing of wafer size from 200mm to 300mm and downscaling of IC design rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment and overlay measurement. In this paper, we present a concept of total process control of alignment and overlay, which we had used to get deeper understanding of our metal process with W-CMP and aluminum sputter. Traditionally, a lot of works are focusing on alignment process control and overlay process control separately. However, based on what we had observed, the final overlay performance is largely affected by the difference between alignment system (alignment mark, alignment sensor and process) and overlay system (overlay mark, overlay sensor and process). Deeper understanding of this difference between alignment and overlay system do help us to get better overlay process control o and process/tool matching.
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Wenzhan Zhou, ZhiQiang Li, Luke Kok Chin Ng, Teng Hwee Ng, Hui Kow Lim, "Total process control of alignment and overlay for metal layer", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.482651; https://doi.org/10.1117/12.482651
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KEYWORDS
Optical alignment

Semiconducting wafers

Overlay metrology

Metals

Sensors

Process control

Tungsten

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