The 2001 edition of the International Technology Roadmap for Semiconductors establishes line-edge roughness (LER) requirements for patterned resist lines. Little is known, however, about how LER affects device performance or about how much LER is acceptable for a given technology. Our work seeks to answer these questions by combining process modeling, three-dimensional (3D) device modeling, and experiment to investigate the amount of LER that can be varied by process conditions and the levels to which LER must be controlled. Our process models show the expected trade-offs between resist diffusion, LER, and resolution, and they show that much of the high-frequency, high-amplitude roughness can be reduced through appropriate etch and implant diffusion processes. The low-frequency roughness, on the other hand, is much harder to eliminate. Experimentally, we have found that the aerial image quality and the etch process have the largest effect on the edge roughness transferred to polysilicon lines, and the roughness after etch is distributed over a broad range of frequencies. The 3D device models indicate that the amount of roughness that gets transferred to the junctions will dominate the electrical behavior, and the effects will likely be different for PMOS devices than NMOS devices.