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26 June 2003 ArF issues of 90-nm-node DRAM device integration
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Recently, the design rule shrinkage of DRAM devices has been accelerated. According to International Technology Roadmap for Semiconductor (ITRS) 2001, 90 nm node will start in 2004. For this achievement, lithography has been standing especially in the forefront and leading the ultra fine patterning technologies in the manufacturing of semiconductor devices. We are now in the moment of transition from the stronghold of KrF to the prospective of ArF. In this paper, we applied ArF process to the real DRAM devices of 90nm node. We proved good pattern fidelity and device performance. The ArF process, however, has still some weak points - resist shrinkage and LER (Line Edge Roughness). Resist shrinkage is very crucial problem for measuring CD. To overcome it, we applied ASC (Anti-Shrinkage Coating) process to ArF resist and improved the CD measurement. LER also becomes an issue, as the design rule is shrink. It is found that they are very dependent on resist type. However, it could be cured effectively by VUV treatment. Finally we will mention the current status of low k1 factor and the future lithographic strategy of which technologies will be most feasible based on current situation.
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Doo-Hoon Goo, Byeong-Soo Kim, Joon-Soo Park, Kwang-Sub Yoon, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han, and Joo-Tae Moon "ArF issues of 90-nm-node DRAM device integration", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003);

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