26 June 2003 Generating sub-30-nm polysilicon gates using PECVD amorphous carbon as hardmask and anti-reflective coating
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Abstract
A PECVD deposited carbon hardmask is combined with dielectric anti-reflective coating (DARC) for the patterning of sub-90nm lines with 248nm lithography. Using this CVD dual layer stack, <1% reflectivity control is demonstrated for both 248nm and 193nm lithography. The film stack is tested with an etch integration scheme to reduce polysilicon gate critical dimension (CD). The dual layer stack can be defined with less than 100nm thick photoresist. Because of the minimal resist required to open the stack, this film stack enables an integration scheme that extends conventional photoresist trim processes up to 70% of the starting line width. In addition to conventional trim process, a resistless carbon mask trim process is investigated to further shrink the gate critical dimension. The results show that the carbon hardmask has greater than 6:1 etch selectivity to polysilicon, enabling the extension of the resist trimming technique to generate sub-30nm structures using 248nm lithography.
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Wei Liu, David Mui, Thorston Lill, May Dongmei Wang, Christopher Bencher, Michael Kwan, Wendy Yeh, Takeaki Ebihara, Toshihiro Oga, "Generating sub-30-nm polysilicon gates using PECVD amorphous carbon as hardmask and anti-reflective coating", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485532; https://doi.org/10.1117/12.485532
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