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26 June 2003 Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node
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Abstract
As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).
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Soo-Han Choi, Ji-Soong Park, Chul-Hong Park, Won-Young Chung, In-sung Kim, Dong-Hyun Kim, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong "Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); https://doi.org/10.1117/12.485397
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