Integrated circuits patterning faces escalating demands challenging the fundamental constraints of the photolithography tools. The challenge is to qualify patterning tools beyond their design objectives, to extend their use for the future manufacturing requirements. To address these challenges, we have adopted a three-step approach: 1) selection of the patterning strategies appropriate for a given set of design rules, 2) projection tool selection to match its capabilities with the process control requirements, and 3) tool’s fine-tuning to maximize patterning process latitude. Step 1 is customary exposure strategy optimization. Steps 2 and 3 go beyond common practice. These two steps rely on aberration residue data obtained by in-situ phase measuring interferometer. The comprehensive, three-step strategy involves all of the key factors impacting the imaging control of critical patterns. In this paper we present the key elements of the patterning strategy and projection lens optimization. We show an example illustrating the three steps of process and tool qualification for aggressive, sub-wavelength design rules. The example presents selection of optimum patterning strategy, the patterning tool selection based on their aberration residuum, and the projection lens residual aberration fine-tuning. The patterning approach resulting from the methodology presented here is compatible with IC manufacturing environment. The approach extends the use of the imaging tools beyond their design objective.