26 June 2003 Limits of strong phase-shift patterning for device research
Author Affiliations +
Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Fritze, Michael Fritze, Renee D. Mallen, Renee D. Mallen, Bruce Wheeler, Bruce Wheeler, Donna Yost, Donna Yost, John P. Snyder, John P. Snyder, Bryan S. Kasprowicz, Bryan S. Kasprowicz, Benjamin George Eynon, Benjamin George Eynon, Hua-Yu Liu, Hua-Yu Liu, } "Limits of strong phase-shift patterning for device research", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485332; https://doi.org/10.1117/12.485332


A litho-only approach to double patterning
Proceedings of SPIE (March 25 2007)
Impact of mask errors on full chip error budgets
Proceedings of SPIE (July 25 1999)
100-nm node lithography with KrF?
Proceedings of SPIE (September 13 2001)

Back to Top