26 June 2003 Optimization of alternating PSM mask process for 65-nm poly-gate patterning using 193-nm lithography
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Abstract
Alternating phase shift mask will be one of the most possible solutions for 65nm technology node as the further delay of 157nm lithography and next generation lithography. In this paper, alternating phase shift mask is used to pattern 65nm poly gate on logic device using 193nm lithography. Double exposure of dark field phase mask and binary trim mask were superimposed on wafers using 193nm scanner. Both mask making process and wafer exposure process are optimized in order to obtain maximum process margin on wafer for 65nm gate CD for pitch of 170nm. The amount of intensity imbalance on alternating phase shift mask with various mask making processes is fully characterized to improve mask making process. Furthermore, the impact of mask making process on process margin is evaluated with and without mask process optimization. The results show that with mask process optimization, large DOF of 0.50μm can be achieved for 65nm line with 170nm pitch. However, without mask process optimization, resolution is limited to 240nm pitch only due to intensity imbalance in 0 degree and 180 degree features. In addition, the study also shows that with alternating phase shift mask, intermediate NA of 0.70 is suitable for 65nm technology as high NA of larger than 0.75 will decrease DOF performance.
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Sia-Kim Tan, Qunying Lin, Liang Choo Hsia, Shi-Chung Sun, "Optimization of alternating PSM mask process for 65-nm poly-gate patterning using 193-nm lithography", Proc. SPIE 5040, Optical Microlithography XVI, (26 June 2003); doi: 10.1117/12.485455; https://doi.org/10.1117/12.485455
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