15 July 2003 CD-SEM measurement line edge roughness test patterns for 193 nm lithography
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Abstract
The measurement of line-edge roughness (LER) has recently become a major topic of concern in the litho-metrology community and the semiconductor industry as a whole, as addressed in the 2001 International Technology Roadmap for Semiconductors (ITRS) roadmap. The Advanced Metrology Advisory Group (AMAG, a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST) has begun a project to investigate this issue and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed solution for implementation. The AMAG group has designed and built a 193 nm reticle that includes structures implementing a number of schemes to intentionally cause line edge roughness of various spatial frequencies and amplitudes. The lithography of these structures is in itself of interest to the litho-metrology community and will be discussed here. These structures, along with several other photolithography process variables, have been used to fabricate a set of features of varying roughness value and structure which span the LER process space of interest. These references are, in turn, useful for evaluation of LER measurement capability. Measurements on different CD-SEMs of major suppliers were used to demonstrate the current state of LER measurement. These measurements were compared to roughness determined off-line by analysis of top-down images from these tools. While no official standard measurement algorithm or definition of LER measurement exists, definitions used in this work are presented and compared in use. Repeatability of the measurements and factors affecting their accuracy were explored, as well as how CD-SEM parameters can affect the measurements.
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Benjamin D. Bunday, Michael Bishop, John S. Villarrubia, Andras E. Vladar, "CD-SEM measurement line edge roughness test patterns for 193 nm lithography", Proc. SPIE 5041, Process and Materials Characterization and Diagnostics in IC Manufacturing, (15 July 2003); doi: 10.1117/12.485234; https://doi.org/10.1117/12.485234
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