10 July 2003 Characterization and modeling of intradie variation and its applications to design for manufacturability
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Abstract
Device scaling increases the impact of within-die variation or mismatch on the performance and yield of many important components of System on Chip (SoC) designs. This has created a need for accurate characterization, modeling, and simulation of mismatch. This paper provides a brief overview of the recent progress in these areas along with an example illustrating the application of these techniques to Design for Manufacturability (DFM) of Ultra Deep Submicron (UDSM) technologies.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sharad Saxena, Sharad Saxena, Carlo Guardiani, Carlo Guardiani, Michele Quarantelli, Michele Quarantelli, Nicola Dragone, Nicola Dragone, Sean Minehane, Sean Minehane, Patrick McNamara, Patrick McNamara, Jeff A. Babcock, Jeff A. Babcock, } "Characterization and modeling of intradie variation and its applications to design for manufacturability", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.497477; https://doi.org/10.1117/12.497477
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