Compression algorithms for dummy-fill VLSI layout data

Robert B. Ellis; Andrew B. Kahng; Yuhong Zheng

doi:10.1117/12.485247

10 July 2003 Compression algorithms for dummy-fill VLSI layout data

Robert B. Ellis, Andrew B. Kahng, Yuhong Zheng

Author Affiliations +

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485247
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

Dummy fill is introduced into sparse regions of a VLSI layout to equalize the spatial density of the layout, improving uniformity of chemical-mechanical planarization (CMP). It is now well-known that dummy fill insertion for CMP uniformity changes the back-end flow with respect to layout, parasitic extraction and performance analysis. Of equal import is dummy fill's impact on layout data volume and the manufacturing handoff. For future mask and foundry flows, as well as potential maskless (direct-write) applications, dummy fill layout data must be compressed at factors of 25 or greater. In this work, we propose and assess a number of lossless and lossy compression algorithms for dummy fill. Our methods are based on the building blocks of JBIG approaches - arithmetic coding, soft pattern matching, pattern matching and substitution, etc. We observe that the fill compression problem has a unique "one-sided" characteristic; we propose a technique of achieving one-sided loss by solving an asymmetric cover problem that is of independent interest. Our methods achieve substantial improvements over commercial binary image compression tools especially as fill data size becomes large.

Citation Download Citation

Robert B. Ellis, Andrew B. Kahng, and Yuhong Zheng "Compression algorithms for dummy-fill VLSI layout data", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485247

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