This paper presents a systematic simulation-based study on the design, performance, and scaling issues of sub-20 nm silicon nanotransistors. 3D-process simulation was used to generate silicon FinFET device structures with fin thickness (Tfin) of 10 to 30 nm, fin height (Hfin) of 50 nm, channel length (Lg) of 10 to 50-nm, and gate oxide thickness (Tox(eff)) of 1.5 nm. 3D-device simulation results show that for n-channel FinFETs with Hfin = 50 nm, threshold voltage (Vth) decreases as Lg decreases and Vth roll-of with decreasing Lg is higher for thicker Tfin devices. The simulated drive current (IDSAT) decreases as Tfin decreases for Lg≤ 25 nm while IDSAT increases as Tfin decreases for Lg ≥ 25 nm. It is, also, found that for the devices with Hfin = 50 nm, the simulated subthreshold swing (S) increases as Lg decreases for all devices with 10 nm ≤ Tfin ≤ 30 nm and approaches to 60 mV/decade for Lg≥ 40 nm. Also, S decreases as Tfin decreases for Lg< 40 nm devices. The simulated data for 20 nm nFinFETs with Hfin = 50 nm, Tfin = 10 nm, and TOX(eff) = 1.5 nm show an excellent device performance with Vth ≡ 0.13 V, IDSAT ≡ 775 μA/μm, Ioff ≡ 3 μA/μm, and S ≡ 83 mV/decade. Finally the simulation results for 20 nm nFinFETs and the conventional nMOSFETs were compared. This study, clearly, demonstrates a superior performance and scalability of FinFETs down to near 10 nm regime.