10 July 2003 Layout optimization at the pinnacle of optical lithography
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This paper attempts to shed more light on the widely acknowledged need to improve the manufacturabilty of itnegrated chip layouts for sub-100nm technology nodes. After reviewing the parametric performance targets and tiem constaints of the 65nm and 45nm technology nodes, the paper elaborates on the principles of popular resolution enhancement techniques, their impact on chip layouts, and the opportunity for borad layout improvement which they afford. Finally, the viability and feasibility of layout optimization based on a design-for-manufacturability mantra and enabled through "radically design restrictions" is explored.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lars W. Liebmann, Greg A. Northrop, James Culp, Leon Sigal, Arnold Barish, Carlos A. Fonseca, "Layout optimization at the pinnacle of optical lithography", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); doi: 10.1117/12.485245; https://doi.org/10.1117/12.485245

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