The complexity in sub-130 nm mask layout often obscures its correctness and true lithography performance. A cost effective solution to ensure high mask performance in lithography is to apply simulation based mask layout verification. Because mask layout verification serves as a gateway to the expensive manufacturing process, the moel used for verification must have superior accuracy across the process window than models used upstream. In this paper, we demonstrate, for the first time, a software system for mask layout verification and optical proximity correction that employs a full resist development model. The new system, LithoScope, predicts wafer pattern by solving optical and resist processing equations on a scale that is until recently considered unpractical. Leveraging the predictive capability of the physical model, LithoScope can perform mask layout verification and optical proximity correction under a wide range of processing conditions and for any reticle enhancement technology without the need for multiple model development. We discuss hotspot detection, line width variation statistics, and chip level process window prediction using a practical cell layout. We show that LithoScope model can accurately describe the resist-intensive poly gate layer patterning by iso-focal optimization. This system can be used to pre-screen and fix mask data problems before manufacturing to reduce the overall cost of the mask and the product.