Resolution enhancement technology requirements for 65-nm node

Armen Kroyan; Hua-Yu Liu

doi:10.1117/12.485486

10 July 2003 Resolution enhancement technology requirements for 65-nm node

Armen Kroyan, Hua-Yu Liu

Author Affiliations +

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485486
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

In this paper, we evaluate various strong and weak resolution enhancement techniques in the context of 65nm technology node requirements. Specifically, we concentrate on a simulation-based performance comparison of the dark-field alternating aperture and chrome-less shifter-shutter phase shifting masks (AAPSM and CLM respectively) for imaging of the critical gate level. Along with the through-pitch aerial image quality, the mask error enhancement factor, proximity effects, and the overall process latitudes are compared. Results show that while there might be multiple approaches in 193nm lithography to pattern isolated and semi-isolated pitches, it is necessary to utilize strong resolution enhancement in order to resovle dense pitches and achieve a sufficient common process performance with required CD control for the 65nm node.

Citation Download Citation

Armen Kroyan and Hua-Yu Liu "Resolution enhancement technology requirements for 65-nm node", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485486

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