As minimum feature size shrinks below 100 nm, all cost components of photomasks: the material, the writing process, the develop/etch process, and the inspection, are skyrocketing. That increase, which impacts new product R&D return on investment, can be mitigated by improving mask first pass yield or synchronizing technology and device requirements with mask shop capabilities. This work is focused on the optimal utilization and tradeoffs of the existing reticle
technology to ensure desired device and circuit parameters. We first look at mask cost increase against the total manufacturing cost, evaluate mask cost by layer, and identify the opportunities to reduce it without compromising product requirements. We then show how integrated simulation (optical combined with electrical) helps estimate the impact of mask CD budget on transistor drive and leakage current, thereby helping justify the need for the tight mask CD
control. For cell level simulation, one would extract FET channel shape from the simulated aerial images to get the parametric data depending on the OPC options at the assumed mask grade and exposure conditions. For chip level simulation, one would derive statistical distribution of device parameters, at the assumed mask grade; parametric yield is then estimated using Monte Carlo analysis, to verify the impact of CD variation of a MOSFET channel across the reticle field. Overall, many challenges of the sub-100 nm reticle manufacturing resulting in high cost can be dealt with by simulation. Integration of simulation tools into design flow would itself become a challenge for computing power and CAD procedures.