Microeconomics of yield learning in semiconductor manufacturing

Kevin M. Monahan

doi:10.1117/12.485288

2 July 2003 Microeconomics of yield learning and process control in semiconductor manufacturing

Kevin M. Monahan

Proceedings Volume 5043, Cost and Performance in Integrated Circuit Creation; (2003) https://doi.org/10.1117/12.485288
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

Citation Download Citation

Kevin M. Monahan "Microeconomics of yield learning and process control in semiconductor manufacturing", Proc. SPIE 5043, Cost and Performance in Integrated Circuit Creation, (2 July 2003); https://doi.org/10.1117/12.485288

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