12 May 2003 Impact of scaling down on 1/f noise in MOSFETs
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Proceedings Volume 5113, Noise in Devices and Circuits; (2003) https://doi.org/10.1117/12.492906
Event: SPIE's First International Symposium on Fluctuations and Noise, 2003, Santa Fe, New Mexico, United States
An overview of the theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependence of 1/f noise in all conduction regime are summarized. Recent experimental studies on 1/f noise in MOS transistors are presented with special emphasis for PMOS from a 90 nm CMOS technology. Gate and drain noise sources are investigated. It is shown that in subthreshold regime drain current noise agrees with carrier number fluctuation model whereas in strong inversion the evolutions can be described by mobility fluctuation model. Gate current noise shows 1/f and white noise. White noise is very close to shot noise, and we have a quadratic variation of 1/f noise with gate current. Coherence measurements show that the increase of drain noise at high gate biases can be attributed to tunneling effects. Input-referred gate noise and the volume trap density can be used as figure of merit. Discrepancies with the ITRS roadmap are discussed.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Matteo Valenza, Matteo Valenza, Alain Hoffmann, Alain Hoffmann, Arnaud Laigle, Arnaud Laigle, Dominique Rigaud, Dominique Rigaud, Mathieu Marin, Mathieu Marin, } "Impact of scaling down on 1/f noise in MOSFETs", Proc. SPIE 5113, Noise in Devices and Circuits, (12 May 2003); doi: 10.1117/12.492906; https://doi.org/10.1117/12.492906

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