8 May 2003 Low-noise SOI Hall devices
Author Affiliations +
Proceedings Volume 5115, Noise and Information in Nanoelectronics, Sensors, and Standards; (2003) https://doi.org/10.1117/12.490185
Event: SPIE's First International Symposium on Fluctuations and Noise, 2003, Santa Fe, New Mexico, United States
Abstract
Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring a wide range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Youcef Haddab, Vincent Mosser, Melanie Lysowec, Jan Suski, Laurent Demeus, Christian Renaux, Stéphane Adriensen, Denis Flandre, "Low-noise SOI Hall devices", Proc. SPIE 5115, Noise and Information in Nanoelectronics, Sensors, and Standards, (8 May 2003); doi: 10.1117/12.490185; https://doi.org/10.1117/12.490185
PROCEEDINGS
8 PAGES


SHARE
Back to Top