Analysis of current-mode flip-flops in CMOS technologies

Raul Jimenez; Pilar Parra; Pedro M Sanmartin; Antonio J. Acosta

doi:10.1117/12.498978

21 April 2003 Analysis of current-mode flip-flops in CMOS technologies

Raul Jimenez, Pilar Parra, Pedro M Sanmartin, Antonio J. Acosta

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498978
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

Switching noise reduction in mixed-mode VLSI circuits is of high importance in mixed-mode applications. The use of current-mode logic circuits, such as Current Steering Logic (CSL) or Current Balanced Logic (CBL) offers advantages in switching noise reduction, since their operation way is based on the use of an almost constant current source. However their usage is limited since they exhibit static power consumption. For this reason, these logic families are only used in those applications where the low-noise requirement becomes critical. Additionally, memory elements are the main source of noise in digital circuits, because they are driven for a few clock signals. In this paper, the analysis of different implementations of memory elements -edge-triggered flip-flops, in current-mode technologies is presented. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 m CMOS technology. The reliability in operation has been also quantified by timing violation parameters measurement. The main results obtained are, on one hand, the selection of a logic family for an specific application and, on the other hand, the selection of an specific flip-flop structure for a optimized parameter option -power, noise or speed. Variations of measured parameters for different operation conditions have been also considered. The novelty of this work lies in this analysis has not been considered before, being usual in other CMOS technologies.

Citation Download Citation

Raul Jimenez, Pilar Parra, Pedro M Sanmartin, and Antonio J. Acosta "Analysis of current-mode flip-flops in CMOS technologies", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498978

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
12 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Logic

Remote sensing

Switching

Transistors

Clocks

CMOS technology

Digital electronics

Show All Keywords

Keywords/Phrases

Search In:

Publication Years