Switching noise reduction in mixed-mode VLSI circuits is of high importance in mixed-mode applications. The use of current-mode logic circuits, such as Current Steering Logic (CSL) or Current Balanced Logic (CBL) offers advantages in switching noise reduction, since their operation way is based on the use of an almost constant current source. However their usage is limited since they exhibit static power consumption. For this reason, these logic families are only used in those applications where the low-noise requirement becomes critical. Additionally, memory elements are the main source of noise in digital circuits, because they are driven for a few clock signals. In this paper, the analysis of different implementations of memory elements -edge-triggered flip-flops, in current-mode technologies is presented. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 m CMOS technology. The reliability in operation has been also quantified by timing violation parameters measurement. The main results obtained are, on one hand, the selection of a logic family for an specific application and, on the other hand, the selection of an specific flip-flop structure for a optimized parameter option -power, noise or speed. Variations of measured parameters for different operation conditions have been also considered. The novelty of this work lies in this analysis has not been considered before, being usual in other CMOS technologies.