Leakage control for deep-submicron circuits

Kaushik Roy; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay

doi:10.1117/12.498181

21 April 2003 Leakage control for deep-submicron circuits

Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498181
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

High leakage current in deep submicron regime is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled every technology generation. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This paper considers various transistor intrinsic leakage mechanisms including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, gate oxide tunneling, and bad-to-band-tunneling and explores different techniques to reduce leakage power consumption for scaled technologies.

Citation Download Citation

Kaushik Roy, Hamid Mahmoodi-Meimand, and Saibal Mukhopadhyay "Leakage control for deep-submicron circuits", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498181

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