21 April 2003 Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoder
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Abstract
This paper focuses on the mapping of low-cost and real-time super-resolution (SR) algorithms onto SOC (System-On-Chip) platforms in order to achieve high-quality image improvements. Low-cost constraints are accomplished by avoiding the need for specific SR hardware, by re-using a video encoder architecture. Only small modifications are needed for: the motion estimator, the motion compensator, image loop memory, etc. This encoder can be used either in compression mode or in SR mode. This video encoder together with the new SR features constitutes an IP block inside Philips Research, upon which several SOC platforms are being developed. Although this SR algorithm has been implemented on an encoder architecture developed by Philips Research it can be easily mapped upon other hybrid video encoder platforms. The results show important improvements in the image quality. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.
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Gustavo Marrero Callico, Gustavo Marrero Callico, Rafael Peset Llopis, Rafael Peset Llopis, Antonio Nunez, Antonio Nunez, Ramanathan Sethuraman, Ramanathan Sethuraman, } "Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoder", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.498868; https://doi.org/10.1117/12.498868
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