21 April 2003 Signaling in the heterogeneous architecture multiprocessor paradigm
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Abstract
This paper discusses and compares solutions for the issue of signalling and synchronization in the heterogeneous architecture multiprocessor paradigm. The on-chip interconnect infrastructure is split conceptually into a data transport network and a signalling network. This paper presents a SystemC based technique for modelling the communication architecture, with different topologies for the synchronization or signalling network. Each topology is parameterised for several communication requirements that define a point in the communication space. A high abstraction model leads to an experimental set-up that eases the analysis of the quantitative and qualitative behaviour of the networks for representative points in the communication space of the system design. The SystemC simulation models developed allow us to obtain information about total simulation time, processing time spent by the coprocessors, data transport time (read/write) used by the coprocessors (including arbitration time), and synchronization time spent by the coprocessors and the network. Another important metric is the coprocessor usage percentage. Results show that splitting data and signalling networks bring additional improvement to the performance of the system. The model applies well when mapping to architectural platforms the application processes expressed by abstract computational models such as Kahn process networks (KPN), synchronous data flow models (SDF), and generalized communicating sequential processes models (CSP).
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Antonio Nunez, Antonio Nunez, Victor Reyes, Victor Reyes, Tomas Bautista, Tomas Bautista, } "Signaling in the heterogeneous architecture multiprocessor paradigm", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); doi: 10.1117/12.499610; https://doi.org/10.1117/12.499610
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