VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing

Walter Stechele

doi:10.1117/12.498499

21 April 2003 VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing

Walter Stechele

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498499
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

A VLSI architecture with flexible, application-specific coprocessors for object based video encoding/decoding is presented. The architecture consists of a standard embedded RISC core, as well as coprocessor modules for macroblock algorithms, motion estimation and bitstream processing. Bitstream decoding involves strong data dependencies, which requires optimized logical partitioning. An optimized instruction set can speed up bitstream decoding by a factor of two. This architecture combines high performance of dedicated ASIC architectures with the flexibility of programmable processors. Dataflow and memory access were optimized based on extensive studies of statistical complexity variations. Results on gate count and clock rate, required for realtime processing of MPEG-4 Core Profile video, are presented, as well as a comparison with software implementations on a standard RISC architecture.

Citation Download Citation

Walter Stechele "VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498499

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