28 August 2003 Anticipating and controlling mask costs within EDA physical design
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Proceedings Volume 5130, Photomask and Next-Generation Lithography Mask Technology X; (2003) https://doi.org/10.1117/12.504270
Event: Photomask and Next Generation Lithography Mask Technology X, 2003, Yokohama, Japan
Abstract
For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael L. Rieger, Michael L. Rieger, Jeffrey P. Mayhew, Jeffrey P. Mayhew, Lawrence S. Melvin, Lawrence S. Melvin, Robert M. Lugg, Robert M. Lugg, Daniel F. Beale, Daniel F. Beale, } "Anticipating and controlling mask costs within EDA physical design", Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); doi: 10.1117/12.504270; https://doi.org/10.1117/12.504270
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